EPFL Lausanne, 30.08.2007, INM 202

Please click on links given below to download available presentation slides.

Program:

8:30	Coffee and cookies (INF 3rd floor)
9:00	Welcome (INM 202)
Session 1: Selected ISS / SSS Research Topics (INM 202)
9:10	ISS Overview / SSS Overview / The Research Cluster UMIC	G. Ascheid / R. Leupers
9:55	"Many Processor" System on Chip	H. Meyr
10:20	Tools and Design Methods for Partially Reconfigurable ASIPs	A. Chattopadhyay K. Karuri
10:45	MPSoC Modeling and Simulation Technologies	T. Kempf
11:10	HySim: A Framework for Fast Simulation of Embedded Software	S. Kraemer
11:35	Discussion
12:00	Update on Noc Activities	S. Murali (INF 331)
12:30	Lunch break at Parmentier Restaurant
Session 2: Selected EPFL Research Topics (INM 202)
14:00	The nano-tera.ch project	G. De Micheli
14:20	LSI Research Activities	D. Atienza
14:45	Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits	P. Brisk
15:15	Exploring New Architectures for Reconfigurable Hardware	A. Cevrero
15:30	CMOS Quantum Imagers for Picosecond Sensing Sensing Applications	E. Charbon
16:00	The HPWREN wireless sensor network	T. Simunic (UCSD)
16:30	Poster session
	1. Application Specific Design of Network-on-Chip	S. Murali (LSI)
	2. A Fast HW/SW FPGA-Based Thermal Emulation Framework for LSI Multi-Processor System-on-Chip	D. Atienza (LSI)
	3. Fault-Tolerant Multi-Level Logic Decoder for Crossbar Memory Arrays	H. Ben Jamaa (LSI)
	4. A Virtual Keyboard based on True 3D Rangefinding	H. Du (Aqua)
	5. A CMOS Microsystem Combining Magnetic Actuation and In-Situ Optical Detection of Microparticles	E. Dupont (Aqua)
	6. Integrated Systems for Ultra-fast Single Photon Detection	C. Niclass (Aqua)
	7. Rethinking Custom ISE Identification: A New Processor-Agnostic Method	A. Verma (LAP)
	8. MOS Current-Mode Logic Standard Cells for Low-Noise Applications?	S. Badel (LSM)
	9. Efficient Modeling and Simulation Methodology for the Design of Mixed-Signal Systems-on-Chips	T. Mähne (LSM)
17:15/17:30	Wrap-Up/End