Synthesis and DSE techniques for matrix-based ambipolar logic architectures

Professor
Department of Electronic, Electrical and Control Engineering
Ecole Centrale de Lyon
Lyon, France

 

Webpage

Friday, 29 September 2017 at 11:20 in room BC 420

 

Abstract:

The advent of high-performance computing architectures is necessary to follow Moore's Law and allow the execution of future software applications both in terms of resolution (audio, video and scientific computing) and in terms of computing power or MIPS (real-time coding/decoding, data encryption/decryption). However, the use of conventional technologies will lead to several device-level hurdles (leakage currents, interconnect limitations, quantum effects …) It is widely recognized that conventional technology scaling will at some point break down in the face of these limits, both for fundamental and for economic reasons. Alternatives must be found, at both architectural and device levels. In this context, the emergence of new switching devices based on nanotubes (CNFET) or nanowires (NWFET) offers the opportunity to provide novel logic building blocks, to explore new possibilities for digital design and consequently to reconsider the paradigms of computing architectures to achieve orders of magnitude improvements in conventional figures of merit.

In this talk, I will look at the emergence of such technologies and assess their potential in the context of computing and communication in future reconfigurable computing platforms. I will firstly present technologies capable of building large regular structures out of silicon nanowires or carbon nanotubes, and then techniques to enable logic functions to be mapped onto them, particularly in the context of reconfigurable applications. Some pointers to the future evolution of these technologies, enabling design techniques and associated architectures will be given, as well as the issues that must be solved before nanoscale computing fabrics become a viable alternative to CMOS.

 

About the speaker:

Ian O'Connor is Professor for Heterogeneous and Nanoelectronics Systems Design in the Department of Electronic, Electrical and Control Engineering at Ecole Centrale de Lyon, France. He is currently head of the Heterogeneous Systems Design group at the Lyon Institute of Nanotechnology. Since 2008, he also holds a position of Adjunct Professor at Ecole Polytechnique de Montréal, Canada. His research interests include novel computing architectures based on emerging technologies, associated with methods for design exploration. He has authored or co-authored around 150 book chapters, journal publications, conference papers and patents, has held various positions of responsibility in the organization of several international conferences and has been workpackage leader or scientific coordinator for several national and European projects. He also serves as an expert with the French Observatory for Micro and Nano Technologies (OMNT), IFIP (International Federation for Information Processing) WG10.5 (Design and Engineering of Electronic Systems), and ALLISTENE (Alliance for digital science and technology).