Logic synthesis for reconfigurable transistors

Professor
Electrical and Computer Engineering
Center for Advancing Electronics Dresden (cfaed)
Technische Universität Dresden
Dresden, Germany
 

 

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Friday, 29 September 2017 at 11:40 in room BC 420

Abstract:

Silicon nanowire reconfigurable field effect transistors (SiNW RFETs) abolish the physical separation of n-type and p-type transistors by taking up both roles in a configurable way within a doping-free technology. However, the potential of transistor-level reconfigurability has not been demonstrated in larger circuits, so far. In this paper, we present first steps to a new compact and efficient design of combinational circuits by employing transistor-level reconfiguration. We contribute new basic gates realized with silicon nanowires, such as 2/3-XOR and MUX gates. Exemplifying our approach with 4-bit, 8-bit and 16-bit conditional carry adders, we were able to reduce the number of transistors to almost one half. With our current case study we show that SiNW technology can reduce the required chip area by 16 %, despite larger size of the individual transistor, and improve circuit speed by 26 %.

 

About the speaker:

Akash Kumar received the joint Ph.D. degree in embedded systems from the National University of Singapore (NUS) and the Eindhoven University of Technology (TUe), Eindhoven, The Netherlands, in 2009. He is currently the Chair for Processor Design at the Center for Advancing Electronics Dresden, Technische Universität Dresden, Germany.

His research interests include design, analysis and resource management of low-power and fault tolerant embedded multiprocessor systems. He has published over 100 papers in leading international electronic design automation journals and conferences on these topics. He has received best paper award nominations including SC 2015, DATE 2015 and FPL 2014. He is also a member of technical program committees of major conferences in the design automation and FPGA design area like, DAC, DATE, CASES, ASPDAC, FPL, FPT, etc.