Senior Manager
Synopsy, California, USA


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Fast Synthesis: DC Explorer Perspective

Thursday, 10 December 2015 at 11:20 in room BC 420

 

Abstract:

Today’s Gigascale designs bring numerous challenges to designers and EDA tools. Advanced designs are larger and more complex than ever before, and synthesis technologies need to constantly evolve to include new innovative algorithms. The race to get products to market first is driving the need to speed up synthesis runtimes for today’s large 10M+ designs while meeting aggressive timing and area goals. In this talk we will focus on the synthesis technologies we have deployed that significantly reduce runtimes by 5-10X.    We will show how DC Explorer improves productivity by enabling designers to efficiently perform early RTL exploration, and create a better starting point for design implementation.

 

About the speaker:

Jovanka Ciric Vujkovic received M.Sc. in 1998 and Ph.D. degree in 2001 in Electrical Engineering from the University of Washington, Seattle, U.S.A., in the areas of Boolean matching and technology mapping. Jovanka was Senior Manager in Synplicity Inc. responsible for Physical synthesis for FPGAs until 2008, continuing her role until 2012 after acquisition of Synplicity by Synopsys. From 2012 until present she is Senior Manager responsible for DC Explorer, early RTL exploration tool for ASIC synthesis in Design Compiler family. Her responsibilities include driving various projects contributing to Synopsys flagship synthesis tools. Jovanka was a member of TPC for DAC 2014 and 2015 in Designer Track. Her interests are in the areas of logic synthesis and physical synthesis and she is holder of two patents.