Thermal-Aware Clock Tree Design

Enrico Macii, Full Professor, Electrical and Computer Engineering, Politecnico di Torino, Turin, Italy

 

Abstract: The existence of non-uniform thermal profiles on the substrate in high performance IC's can significantly impact the performance of global on-chip interconnects. This issue is further exacerbated due to aggressive scaling of IC's and various other factors such as dynamic power management (clock gating), different operational modes of functional blocks (active, standby and sleep) and non-uniform gate level switching activity to name a few. Also in high performance systems one of the most important problems is clock skew minimization since it has a direct impact on the maximum operating frequency of the system. Since clocks are routed across the entire chip, the presence of thermal gradients can significantly alter their characteristics considering that resistivity of wires increases linearly as the temperature increases. This often results in failure to meet original timing constraints thereby rendering the original topology unusable. Therefore it is necessary to perform a temperature aware re-embedding of the original topology to meet timing under these temperature effects. This work primarily explores the above mentioned issues in detail along with proposing methodologies to alter the original clock tree topology to compensate for such temperature effects and as a result also meet timing constraints.

About the speaker: Enrico Macii was born in Torino, Italy, in 1966. He holds a Dr.Eng. degree in Electrical Engineering from Politecnico di Torino, a Dr.Sc. degree in Computer Science from Universita' di Torino, and a Ph.D. degree in Computer Engineering from Politecnico di Torino. From May 1991 through August 1991 he was a Visiting Faculty at the University of California at Los Angeles, and from September 1991 through September 1994 he was an Adjunct Faculty at the University of Colorado at Boulder. Currently, he is a Full Professor of Electrical and Computer Engineering at Politecnico di Torino.

His research interests include several aspects of the computer-aided design of digital integrated circuits and systems, with particular emphasis on logic synthesis, optimization, testing, and formal verification. In the last few years, he has focussed his attention to the study and development of methodologies, algorithms and tools for power estimation and optimization of systems described at various levels of the design hierarchy. He has authored or co-authored over 200 journal and conference articles, as well as book chapters, in the areas above, and he has received the Best Paper Award for an article presented at the 1996 IEEE EuroDAC: European Design Automation Conference.

 

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