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Valentina Ciriani
Logic Synthesis via Boolean Relations
Thursday, 10 December 2015 at 11:40 in room BC 420
Abstract:
In this work, we investigate how to use the flexibility of Boolean relations in order to obtain a compact algebraic representation of a logic function. Boolean relations allow to represent generalized don't care conditions and can be exploited to efficiently model several Boolean optimization problems. Exploiting this flexibility, we show how to formally model and efficiently minimize several bounded-level logic circuits.
About the speaker:
Valentina Ciriani received the Laurea degree and the Ph.D. degree in Computer Science from the University of Pisa, Italy, in 1998 and 2003, respectively. Currently, she is an Associate Professor with the Department of Computer Science, University of Milano. Her research interests include algorithms and data structures, as well as combinational logic synthesis, VLSI design of low power circuits and testing of Boolean circuits. She has authored or coauthored more than 70 research papers, published in international journals, conference proceedings, and books chapters.
Secondary navigation
- Layout synthesis: A golden DA topic
- EPFL Workshop on Logic Synthesis & Verification
- Luca Amaru
- Luca Benini
- Robert Brayton
- Maciej Ciesielski
- Valentina Ciriani
- Jovanka Ciric-Vujkovic
- Jason Cong
- Jordi Cortadella
- Giovanni De Micheli
- Antun Domic
- Rolf Drechsler
- Henri Fraisse
- Paolo Ienne
- Viktor Kuncak
- Enrico Macii
- Igor Markov
- Steven M. Nowick
- Tsutomu Sasao
- Alena Simalatsar
- Leon Stok
- Dirk Stroobandt
- Tiziano Villa
- Functionality-Enhanced Devices Workshop
- Nanotechnology for Health
- Secure Systems Design
Presentation Slides
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