Professor
Department of Electrical Engineering
University of Southern California, Los Angeles, CA - USA
Webpage

Lecture 1: Tuesday, 15 July 2008 (14h00-15h00) CO3

Minimizing Leakage Power in CMOS: Technology Issues
In many new designs, the leakage component of power consumption is comparable to the dynamic component. Many reports indicate that 50% or even higher percentage of the total power consumption is due to the leakage of transistors and this percentage will increase with technology scaling unless effective techniques are used to bring leakage under control. This talk will focus on circuit techniques and design methods to accomplish this goal. The first part of the presentation provides an overview of basic physics and technology, and scaling trends that have resulted in the significant increase in sub-threshold and gate leakage currents. The part provides an in-depth description of multiple, Vdd, multiple-Vt, and multiple Tox techniques for leakage minimization in light of process variations and substrate temperature changes.


Lecture 2: Tuesday, 15 July 2008 (15h15-16h15) CO3

Minimizing Leakage Power in CMOS: Design Optimization Techniques
The second part of this presentation describes a number of design optimization techniques for controlling leakage current, including, state assignment, technology mapping, and precomputation-based signal guarding. It will also present runtime mechanisms for leakage control including body bias control, transition to minimum leakage state, and power gating.

About the speaker:
Massoud Pedram obtained his B.S. degree in Electrical Engineering from the California Institute of Technology in 1986. Subsequently, he received M.S. and Ph.D. in Electrical Engineering and Computer Sciences from the University of California, Berkeley in 1989 and 1991, respectively. In September 1991, he joined the Department of Electrical Engineering at the University of Southern California where he is currently a professor and Chair of the Computer Engineering division. Dr. Pedram is a recipient of the National Science Foundation's Young Investigator Award (1994) and the Presidential Early Career Award for Scientists and Engineers (a.k.a. the Presidential Faculty Fellows Award) (1996). He has published more than 300 journal and conference papers and written four books on various aspects of low power design.

His research specializations include:

1. Dynamic Power Management and Power-Aware Design
2. Architectural and RT-Level Power Analysis, Design, and Optimization
3. Ultra Low Power Circuit Design Techniques
4. Power Conversion and Regulation Technologies
5. Smart Battery Design
6. Physical Design Optimization and Logic Synthesis Techniques
7. Design Automation Tools and Flows for Performance and Reliability Optimization of VLSI Circuits
8. Signal Integrity Analysis and Optimization of VLSI Interconnects
9. Power-Aware Wireless Sensor Networks
10. Nanotechnology and Beyond CMOS Technologies