Position statement:

Design for low power & High performance DRAM

Recently semiconductor industry is at peak of development on emerging applications under the IT megatrends such as Internet of Everything, Wearable Device, Connected Car, etc. Such an IT megatrend requires miniaturization, low power and high performance for system, therefore memory chip manufactures mainly focus on the development to meet such system requirements. Especially for DRAM as one of the most important roles in the system, improving the bandwidth and realizing the ultra-low power efficiency have become the key technology enablers for accomplishment than ever.

In memory semiconductor industry, with continuous scaling, development for device and process is actively ongoing to realize low power and high performance. For example, development of each HKMG/FDSOI, FinFET CMOS, and Low k IMD is the key task as the new scaling techniques and they would provide an excellent chance to improve memory system. However, below 20nm, there are still lots of unsolved and challenging issues such as cost, development duration to overcome, so that it still needs aggressive research and development for mass production. 

To enhance memory design, there are plenty of ongoing research for low power and high performance. Mobile DRAM like LPDDR4 interlocking with the system is mainly focused on realizing both lower power and higher performance, and deciding the new target application based on the megatrend.

The circuit technology for energy efficiency such as DBB (Dynamic Body Bias), Multi Vth, and power gating is applied primarily to reduce leakage current and it will keep focusing on minimizing power consumption. To achieve energy minimization, it is the right moment for developing new design scheme to reduce both dynamic and leakage power.

In the point of high performance, it puts so much work on 3D stacking technology such as HBM, Wide IO, and HMC utilizing TSV technology to improve the performance with the increased number of I/O. However, in accordance with I/O increase, level of difficulty and manufacturing costs also sharply increased. Therefore, it is currently developing for both reducing the number of I/Os and improving the speed simultaneously. Finding an optimizing point from the relationship between 3D DRAM performance and the number of I/Os will be a very critical project.

Lastly, all the countermeasures for energy efficiency and high bandwidth should be established with less cost and higher reliability as the first consideration. Hence, New design scheme is required to minimize the defect rate, and maximize reliability & cost reduction by utilizing concepts such as On-Chip ECC, and PPR(Post Package Repair).

To encapsulate what I described above, new design scheme or design orientation need to be discussed satisfying the requirements of low power, high performance and reliability.
 

About the panel member:

Seok-Hee Lee received the B.S. and M.S. degrees in Materials Science and Engineering from Seoul National University, Seoul, Korea, in 1988 and 1990, respectively, and the Ph.D. degree in Materials Science and Engineering from Stanford University, Stanford, CA. in 2000. Since February 2013, he has been with SK Hynix, as Senior VP and head of R&D division.

From 1990 to 1995, he was with the Advanced Semiconductor Development group, Hyundai Electronics (now SK Hynix), Korea, where he worked in the area of gate oxide scaling and reliability. In 1994, he discovered a new breakdown mechanism, “quasi-breakdown (also known as soft-breakdown),” in ultra-thin gate oxide regime.  The research was reported at IEDM94 and has since developed into a new area of study in oxide reliability.  This work has been cited in more than 100 research papers since then.

From 2000 to 2010, he was with the Portland Technology Development group, Intel Corporation, Hillsboro, OR, where he worked on process integration and yield on Intel’s 130-, 90-, and 65-nm advanced CMOS logic technologies. Most recently, he managed a process integration team responsible for developing 32-nm logic process technology.

Dr. Lee has received the Intel Achievement Award three times (Intel’s highest recognition for technical achievement) and 11 Intel Divisional Recognition Awards for his technical achievements in transistor and process development.

From 2010 to 2013, he was with the the department of electrical engineering in KAIST, Korea, as an associate professor. His main research was on nano-scale devices and fabrication. Professor Lee received the best teaching award in 2011.

He was a committee member for CMOS devices and technology subcommittee for 2008-2009 IEDM, the chair for the same subcommittee in 2010 IEDM, Asian arrangement chair for 2011 and 2012 IEDM, and emerging technology chair for 2013 IEDM. He is also serving International Conference on Solid State Devices and Materials (SSDM) as a steering committee member for 2011-2014 meetings.