Associate Professor
Robust Systems Group, Director
Departments of Electrical Engineering and Computer Science
Stanford University, Stanford, CA - USA

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Carbon Nanotube Computing

Tuesday, 11 October 2016 at 9:40

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The computing demands of future abundant-data applications far exceed the capabilities of today’s electronics, and cannot be met by isolated improvements in transistor technologies, memories, or integrated circuit (IC) architectures alone. Transformative nanosystems, which leverage the unique properties of emerging nanotechnologies to create new IC architectures, are required to deliver unprecedented performance and energy efficiency. However, emerging nanomaterials and nanodevices face major obstacles such as inherent imperfections and variations. Thus, realizing working circuits, let alone transformative nanosystems, has been infeasible.

Carbon nanotube field-effect transistors (CNFETs) are a leading candidate for building energy-efficient and high-performance digital systems. Unfortunately, substantial imperfections and variations inherent to carbon nanotubes (CNTs), combined with low current densities, restricted prior CNFET demonstrations to stand-alone transistors or logic gates, with severely limited performance, yield, and scalability. A new imperfection-immune paradigm overcomes these challenges through a combination of new CNT processing techniques and CNFET circuit design solutions. This paradigm transforms CNTs from solely a scientifically-interesting material into working nanosystems such as the first microprocessor built entirely using CNFETs.  These are the first system-level demonstrations among promising emerging nanotechnologies for high-performance and highly energy-efficient digital systems.

CNTs also enable new computing architectures, referred to as N3XT (Nano-Engineered Computing Systems Technology), that are otherwise difficult to realize using conventional silicon technologies. Our N3XT approach creates new architectures for computation immersed in memory through ultra-dense (e.g., monolithic) three-dimensional integration of CNFET logic and high-density non-volatile resistive and magnetic memories. N3XT hardware prototypes represent leading examples of transforming scientifically-interesting nanomaterials and nanodevices into actual nanosystems. Compared to conventional approaches, N3XT architectures promise to improve the energy efficiency of abundant-data applications significantly, in the range of three orders of magnitude, thereby enabling new frontiers of applications for both mobile devices and the cloud.

About the speaker:

Subhasish Mitra directs the Robust Systems Group in the Department of Electrical Engineering and the Department of Computer Science of Stanford University, where he is the Chambers Faculty Scholar of Engineering. Before joining Stanford, he was a Principal Engineer at Intel. 

Prof. Mitra's research interests include robust systems, VLSI design, CAD, validation and test, nanosystems, and emerging neuroscience applications.  His X-Compact technique for test compression has been key to cost-effective manufacturing and high-quality testing of a vast majority of electronic systems, including numerous Intel products. X-Compact and its derivatives have been implemented in widely-used commercial Electronic Design Automation tools. He, jointly with his students and collaborators, demonstrated the first carbon nanotube computer, and it was featured on the cover of NATURE. The US NSF presented this work as a Research Highlight to the US Congress, and it also was highlighted as "an important, scientific breakthrough" by the BBC, Economist, EE Times, IEEE Spectrum, MIT Technology Review, National Public Radio, New York Times, Scientific American, Time, Wall Street Journal, Washington Post, and numerous other organizations worldwide.

Prof. Mitra's honors include the Presidential Early Career Award for Scientists and Engineers from the White House, the highest US honor for early-career outstanding scientists and engineers, the ACM SIGDA/IEEE CEDA A. Richard Newton Technical Impact Award in Electronic Design Automation, "a test of time honor" for an outstanding technical contribution, the Semiconductor Research Corporation's Technical Excellence Award, and the Intel Achievement Award, Intel’s highest corporate honor.  He and his students published several award-winning papers at major venues: IEEE/ACM Design Automation Conference, IEEE International Solid-State Circuits Conference, IEEE International Test Conference, IEEE Transactions on CAD, IEEE VLSI Test Symposium, Intel Design and Test Technology Conference, and the Symposium on VLSI Technology. At Stanford, he has been honored several times by graduating seniors "for being important to them during their time at Stanford."

Prof. Mitra has served on numerous conference committees and journal editorial boards. He served on DARPA's Information Science and Technology Board as an invited member. He is a Fellow of the ACM and the IEEE.