Position statement:

Five Grand Challenges for Circuits in Emerging Nanotechnologies

Nanotechnologies offer a broad spectrum of opportunities for the realization of data processing systems. Answers to current grand challenges can be found at many levels: the device level (optical interconnects, magnetic memories, resistive memories, spintronics), the information representation level (spin, phase, polarization ...) and the computational paradigm level (neuromorphic architectures, reversible logic ...) to name but a few. In this position statement I will briefly outline some challenges facing circuit designers to improve logic performance with nanotechnologies over conventional techniques.

1. Reduce energy consumption and increase energy efficiency of data processing systems. Currently, the energy required for the switching a bit is of the order of 1aJ, while that required for the communication of a bit is of the order of 1pJ/mm. At the scale of 10G transistors/cm², operating above 1GHz and with a total interconnect length beyond 1km/cm², silicon power density limits (100W/cm²) are easily reached and lead to dark silicon, a barrier to the pursuit of higher performance. And further, there is room to scale: the Landauer limit predicts that switching a bit at room temperature could be done with just 3zJ/bit, three orders of magnitude below current levels.

2. Use technology to its limit throughout its life cycle, and ensure reliable system operation in the presence of both unreliable devices and increasing complexity. The cost of a zero-defect technology based on photolithography is all but impossible to support at the nanoscale and other means to improve reliability, such as hardware regularity, or ultra-fine grain reconfigurability, are to be considered.

3. Develop hardware solutions for ZB (10e¹⁸ bytes) data storage suited to the big data era. This is not just a problem in terms of memory capacity for existing media, but is also and especially a problem in terms of speed of access, compounded by the difficulty of structuring data. Many good new technological choices exist (MRAM, PCRAM, CBRAM, memristor ...) and could provide radically different structures for memory hierarchy compatible with big data.

4. Develop systems adapted to new services (M2M, IoT, cloud computing ...) The advent of these new models of data processing relies on ultra-low power embedded systems to sense and interact with the physical environment in real time without intervention, as well as high-performance datacenters to handle and store the resulting exabytes of data in a secure way. These systems also need communication infrastructures capable of carrying hundreds of Mbps per mobile terminal or hundreds of Gbps per node.

5. Promote and exploit the potential of 3D heterogeneous (More than Moore) integration through the development of micro-nano-electronic architectures exploiting micro-mechanical / optical / thermal / fluidic / micro-biological sensors and actuators. This ultimate level of integration provides access to enhanced performance compared to state of the art (in terms of reduced form factor, cost, energy consumption and increased functionality, performance) and targets system miniaturization ("functional diversification" for sensor network nodes including integrated energy harvesting, for example) and/or hybridization with specific non-electronic functions to meet the demands of energy consumption, reliability and adaptability ("equivalent scaling" in computing to overcome the limits of CMOS technology).

About the panel member:

Ian O'Connor (IEEE S'95-M'98-SM'07) is Professor for Heterogeneous and Nanoelectronics Systems Design in the Department of Electronic, Electrical and Control Engineering at Ecole Centrale de Lyon, France. He is currently head of the Heterogeneous Systems Design group at the Lyon Institute of Nanotechnology. Since 2008, he also holds a position of Adjunct Professor at Ecole Polytechnique de Montréal, Canada. His research interests include novel computing architectures based on emerging technologies, associated with methods for design exploration. He has authored or co-authored around 150 book chapters, journal publications, conference papers and patents, has held various positions of responsibility in the organization of several international conferences and has been workpackage leader or scientific coordinator for several national and European projects. He also serves as an expert with the French Observatory for Micro and Nano Technologies (OMNT), IFIP (International Federation for Information Processing) WG10.5 (Design and Engineering of Electronic Systems), and ALLISTENE (Alliance for digital science and technology).