Professor
Integrated Systems Laboratory
Digital Circuits and Systems Group
ETHZ, Zurich, Switzerland

 

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Sub-pj per Operation Parallel Computing in CMOS: Foundations to Implementation

Tuesday, 11 October 2016 at 8:45

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Abstract:

The  "internet of everything" envisions trillions of connected objects loaded with high-bandwidth sensors requiring massive amounts of local signal processing, fusion, pattern extraction and classification. From the computational viewpoint, the challenge is formidable and can be addressed only by pushing computing fabrics toward massive parallelism and brain-like energy efficiency levels. CMOS technology can still take us a long way toward this vision.

Our recent results with the  open-source PULP (parallel ultra-low power) chips demonstrate that pj/OP (GOPS/mW) computational efficiency is within reach even in consolidated 28nm CMOS FDSOI technology. However, the energy efficiency boost coming from scaling to next two technology nodes is moderate
at best, and no single technology silver bullet is in sight beyond CMOS.

This talk will look at the next 1000x of energy efficiency improvement,  which will require heterogeneous 3D integration,  mixed-signal preprocessing, event-based approximate computing and non-Von-Neumann architectures for scalable acceleration.  The goal of deep sub-pJ computing is achievable in the next decade and  there are several clear signs on the path that we need to follow to achieve it.

About the speaker:

Luca Benini is Full Professor at the University of Bologna and he is the chair of Digital Circuits and Systems at ETHZ.

He has served as Chief Architect for the Platform2012/STHORM project in STmicroelectronics, Grenoble in the period 2009-2013. He has held visiting and consulting researcher positions at EPFL, IMEC, Hewlett-Packard Laboratories, Stanford University.

Dr. Benini's research interests are in energy-efficient system design and Multi-Core SoC design. He is also active in the area of energy-efficient smart sensors and sensor networks for biomedical and ambient intelligence applications. In these areas he has coordinated tens of funded projects, including an on-going ERC Advanced Grant on Multi-scale thermal management of Computing Systems.

He has published more than 700 papers in peer-reviewed international journals and conferences, four books and several book chapters (h-index=86 on Google Scholar). He is a Fellow of the IEEE and a member of the Academia Europaea and has served for two terms as a member of the steering board of the ARTEMISIA European Association on Advanced Research & Technology for Embedded Intelligence and Systems.