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Luca Amaru
Advances in Industrial Logic Synthesis
Senior II R&D Engineer
Design Group, Synopsys Inc.
Mountain View, California, USA
Thursday, 28 September 2017 at 11:20 in room BC 420
Abstract:
Logic synthesis is a key design step which optimizes abstract circuit representations and links them to technology. In this talk, we present recent innovations in industrial logic synthesis, with a focus on data structures and algorithms for optimization. First, we tackle fundamental challenges in exact delay synthesis. Then, we improve the efficiency of Boolean resynthesis engines. We evaluate the impact of both innovations, and show sensible gains in quality-of-results, over industrial benchmarks, at small runtime cost. These results confirm the continuing importance of logic optimization and synthesis in EDA, and exhibit room for improvements in other logic applications.
About the speaker:
Luca Amaru is Senior II R&D Engineer in the Design Group of Synopsys Inc., Mountain View, CA, USA. He is responsible for designing efficient data structures and algorithms for logic synthesis tools.
Previously, he was research assistant at EPFL, Integrated Systems Laboratory, Lausanne, Switzerland (2011-2015), and visiting researcher at Stanford University, Palo Alto, CA, USA (2014).
Dr. Amaru received his PhD degree in Computer Science from EPFL, Lausanne, Switzerland (2015). He received his double Master's Degree in Electronic Engineering, with honors, from Politecnico di Torino, Turin, Italy, and Politecnico di Milano, Milan, Italy (2011). He received his Bachelor's Degree in Electronic Engineering, with honors, from Politecnico di Torino, Turin, Italy (2009).
At present, Dr. Amaru is author or coauthor of 70 scientific articles and inventor or coinventor of 8 patents
Secondary navigation
- EPFL Workshop on Logic Synthesis and Emerging Technologies
- Luca Amaru
- Luca Benini
- Giovanni De Micheli
- Srini Devadas
- Antun Domic
- Rolf Drechsler
- Pierre-Emmanuel Gaillardon
- Jie-Hong Roland Jiang
- Akash Kumar
- Shahar Kvatinsky
- Yusuf Leblebici
- Shin-ichi Minato
- Alan Mishchenko
- Vijaykrishnan Narayanan
- Ian O'Connor
- Andre Inacio Reis
- Martin Roetteler
- Julien Ryckaert
- Mathias Soeken
- Christof Teuscher
- Zhiru Zhang
- Symposium on Emerging Trends in Computing
- Layout synthesis: A golden DA topic
- EPFL Workshop on Logic Synthesis & Verification
- Luca Amaru
- Luca Benini
- Robert Brayton
- Maciej Ciesielski
- Valentina Ciriani
- Jovanka Ciric-Vujkovic
- Jason Cong
- Jordi Cortadella
- Giovanni De Micheli
- Antun Domic
- Rolf Drechsler
- Henri Fraisse
- Paolo Ienne
- Viktor Kuncak
- Enrico Macii
- Igor Markov
- Steven M. Nowick
- Tsutomu Sasao
- Alena Simalatsar
- Leon Stok
- Dirk Stroobandt
- Tiziano Villa
- Symposium on Emerging Trends in Electronics
- Raul Camposano
- Anantha Chandrakasan
- Jo De Boeck
- Gerhard Fettweis
- Steve Furber
- Philippe Magarshack
- Takayasu Sakurai
- Alberto Sangiovanni-Vincentelli
- Ken Shepard
- VENUE
- Panel on Circuits in Emerging Nanotechnologies
- Panel on Emerging Methods of Computing
- Panel on The Role of Universities in the Emerging ICT World
- Panel on Design Challenges Ahead
- Panel on Alternative Use of Silicon
- Nano-Bio Technologies for Lab-on-Chip
- Functionality-Enhanced Devices Workshop
- More Moore: Designing Ultra-Complex System-on-Chips
- Design Technologies for a New Era
- Nanotechnology for Health
- Secure Systems Design
- Surface Treatments and Biochip Sensors
- Security/Privacy of IMDs
- Nanosystem Design and Variability
- Past Events Archive
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Venue
All talks will take place at EPFL room BC 420. Please click here to go to the interactive EPFL map.