Professor and Department Head
Department of Electrical Engineering and Computer Science
Massachusetts Institute of Technology, Cambridge, MA, USA

 

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Ultra-Low-Power Networked Systems

A variety of emerging applications will require operation from tiny energy sources and energy harvesting. Example systems include networked sensors for industrial monitoring, next-generation implanted and body-worn medical electronics, and location aware devices. These systems will drive the next generation of ultra-low-power electronics for sensing and interfaces, signal processing, energy conversion, and wireless communications. The entire system must operate from nanowatts to microwatts to be powered by energy-harvesting sources such as vibrations, body heat or even biological energy sources. The focus of this presentation is on circuit and system approaches to realize an ultra-low-power electronic system.

As an example of nano-powered harvesting, the talk will highlight extracting power from the endo-cochlear potential (EP), a 70-100mV potential inside the mammalian inner ear. The total extractable power from the EP is limited to the nanowatt range. Operating at these power levels requires aggressive fine-grained duty-cycling. The energy converter, based on a low switching frequency boost converter, uses ultra-low-power digital control and efficient leakage control techniques to achieve low-quiescent power and high-efficiency operation.  A low-duty cycle transmitter for the implant leverages circuit and system techniques to achieve an average power consumption of less than 100pW. 

System-level energy-efficiency is achieved through exploiting application attributes (e.g., signal statistics). This presentation will cover low-power techniques including ultra-low-voltage digital circuit operation, application-specific architectures, data-driven processing, and computation vs. communication trade-off. A range of techniques to exploit data dependencies can be used to save energy from low-level data dependent memories and converter architectures that exploit signal correlations to system-activity monitors. To achieve adaptive energy minimization, integrated digital energy monitors are needed. A processor with embedded energy monitors will be discussed, which allows adaptive energy scaling and configuration.

A complete low-power cochlear implant that requires no external hardware will be presented. The implant can be wirelessly charged and can operate for about eight hours on each charge. The implantable acoustic sensing is achieved by interfacing the SoC to a piezoelectric sensor that is mounted at the umbo of the malleus within the middle ear. The system enables system power scalability by scaling the number of spectral channels and uses energy-optimal stimulation waveform.  A system-level approach is used to achieve fully implanted operation using wireless charging.

About the speaker:

Anantha P. Chandrakasan received the B.S, M.S. and Ph.D. degrees in Electrical Engineering and Computer Sciences from the University of California, Berkeley, in 1989, 1990, and 1994 respectively. Since September 1994, he has been with the Massachusetts Institute of Technology, Cambridge, where he is currently the Joseph F. and Nancy P. Keithley Professor of Electrical Engineering.

He was a co-recipient of several awards including the 1993 IEEE Communications Society's Best Tutorial Paper Award, the IEEE Electron Devices Society's 1997 Paul Rappaport Award for the Best Paper in an EDS publication during 1997, the 1999 DAC Design Contest Award, the 2004 DAC/ISSCC Student Design Contest Award, the 2007 ISSCC Beatrice Winner Award for Editorial Excellence and the ISSCC Jack Kilby Award for Outstanding Student Paper (2007, 2008, 2009). He received the 2009 Semiconductor Industry Association (SIA) University Researcher Award. He is the recipient of the 2013 IEEE Donald O. Pederson Award in Solid-State Circuits.

His research interests include micro-power digital and mixed-signal integrated circuit design, wireless microsensor system design, portable multimedia devices, energy efficient radios and emerging technologies. He is a co-author of Low Power Digital CMOS Design (Kluwer Academic Publishers, 1995),  Digital Integrated Circuits (Pearson Prentice-Hall, 2003, 2nd edition), and Sub-threshold Design for Ultra-Low Power Systems (Springer 2006). He is also a co-editor of Low Power CMOS Design (IEEE Press, 1998), Design of High-Performance Microprocessor Circuits (IEEE Press, 2000), and Leakage in Nanometer CMOS Technologies (Springer, 2005).

He has served as a technical program co-chair for the 1997 International Symposium on Low Power Electronics and Design (ISLPED), VLSI Design '98, and the 1998 IEEE Workshop on Signal Processing Systems. He was the Signal Processing Sub-committee Chair for ISSCC 1999-2001, the Program Vice-Chair for ISSCC 2002, the Program Chair for ISSCC 2003, the Technology Directions Sub-committee Chair for ISSCC 2004-2009, and the Conference Chair for ISSCC 2010-2014. He is the Conference Chair for ISSCC 2015. He was an Associate Editor for the IEEE Journal of Solid-State Circuits from 1998 to 2001. He served on SSCS AdCom from 2000 to 2007 and he was the meetings committee chair from 2004 to 2007. He was the Director of the MIT Microsystems Technology Laboratories from 2006 to 2011. Since July 2011, he is the Head of the MIT EECS Department.