Silicon Scaling by exploiting the 3rd dimension

Distinguished Member of Technical Staff
imec
Leuven, Belgium

 

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Friday, 29 September 2017 at 14:20 in room BC 420

Abstract:

By 2020 Moore’s Law will see an unprecedented pressure. It is already a fact that since the 20nm node, the happy scaling era where dimensional scaling was the fuel to generate cheaper, faster and more power efficient technology nodes ran out of steam. Today, technologists use all possible “technology enablers” or “boosters” to keep the prophecy alive. These techniques trade design requirements with specific technology capabilities in a so-called design-technology co-optimization. Nevertheless, these specific techniques are not endless and soon the “third dimension” will be inevitable to keep density scaling. However, although the migration from 2D to 3D structures worked well in memory technologies, there are number of obstacles that will need to be overcome when applied to logic technologies. Moreover the disruptive migration to 3D is far from straightforward for an industry that is built on a complex eco-system of technology, fabless and EDA companies.

About the speaker:

Julien Ryckaert received the M.Sc. degree in Electrical Engineering from the University of Brussels (ULB), Belgium, in 2000 and the PhD degree from the Vrije Universiteit Brussel (VUB) in 2007. He joined imec as a mixed-signal designer in 2000 specializing in RF transceivers, ultra-low power circuit techniques and analog-to-digital converters. In 2010 he joined the process technology division in charge of design enablement for 3D stacking technology. In 2013, he was responsible for imec’s Design-Technology Co-Optimization (DTCO) platform for advanced CMOS technology nodes focusing on 10nm and 7nm nodes. Since 2016 he is a Distinguished Member of the Technical Staff in charge of the 3D Logic program targeting scaling beyond the 5nm technology node. Julien Ryckaert has authored and co-authored more than 50 peer-reviewed Journal and conference papers. He has served as TPC member of the Asian Solid-State Circuits Conference.