Complete FPGA-Based Emulation Framework for Multi-Processor System-on-Chip

David Atienza, PhD, Post-Doc at LSI-EPFL.

 

Abstract: With the growing complexity in consumer embedded products and the improvements in process technology, Multi-Processor System-On-Chip (MPSoC) architectures have become widespread. These new systems are very complex to design as they must execute multiple complex real-time applications (e.g. video processing, or videogames), while meeting several additional design constraints (e.g. energy consumption or time-to-market). Therefore, mechanisms to efficiently explore the different possible HW-SW design interactions in complete MPSoC systems in an early stage of the design process are in great need.

For this purpose several MPSoC simulators have been proposed, both at transaction and cycle-accurate levels using HDL languages and SystemC. Although they achieve accurate estimations, they are limited in performance (circa 10-100 Khz) due to signal management overhead. Thus, such environments cannot be used to analyze MPSoC solutions with complex embedded applications and large inputs to cover the variations in data loads at run-time. Moreover, higher abstraction levels simulators attain faster simulation speeds, but at the cost of a significant loss of accuracy. Hence, they are not suitable for fine-grained architectural tuning.

In this talk, we present the current status of a new complete FPGA-based emulation framework developed as a joint project between LSI/EPFL, DACYA/UCM and DEIS/UNIBO, which allows designers to rapidly explore a large range of MPSoC design alternatives at the cycle-accurate level. Our results show that the proposed framework is able to extract a number of critical statistics from processing cores, memory and interconnection systems, with a speed-up of three orders of magnitude compared to state-of-the-art cycle-accurate MPSoC simulators.
 

About the speaker: David Atienza Alonso recieved his BS, MS and PhD degrees in Computer Engineering from Complutense University of Madrid (UCM) in 1999, 2001 and 2005 respectively.

He currently holds a Post-Doc position at the Integrated Systems Laboratory (LSI) at EPFL. He also holds the position of invited Assistant Professor at the Computer Architecture and Automation Department (DACYA) of Complutense University of Madrid (UCM), Spain. Also, he is currently scientific counselor of long-time research at the Digital Design Technology (DDT) Group of Inter-University Micro-Electronics Center (IMEC), Leuven, Belgium.

His research interests include several aspects of design technologies for integrated circuits and systems, with particular emphasis on scalable interconnection paradigms for multi-Processors System-on-Chip: Networks-On-Chip (NoC), dynamic memory management, system-level design and low-power design.

 

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