Professor
Department of Computer Science
University of California, Los Angeles, CA - USA
Webpage

Lecture 1: Wednesday, 16 July 2008 (14h00-15h00) CO3

Design for Nanotechnologies and 3D ICs
In this talk, I shall first give an overview of the research in my group on design for nanotechnologies, as part of the ongoing project funded by the National Science Foundation jointly with Kang Wang (UCLA EE), Tim Cheng and Evelyn Hu (UCSB ECE). While most innovations in nanotechnology at this stage are primarily at the level of individual devices, we believe that it is at the systems level where the true potential of nanotechnology can be realized. Our research focuses on three areas - variability, reliability, and complexity of design for nanotechnologies and I shall highlight our progress in each of the three areas.

In the second part of my talk, I shall present a thermal-aware 3D IC physical design system developed at UCLA in the past five years, including 3D floorplanning, 3D placement, and 3D routing with thermal via planning and insertion. I shall present our ongoing work on 3D microarchitecture exploration, based on the detailed physical prototyping using our 3D physical design tool and cycle-accurate architecture simulation. Preliminary study shows that for a simple out-of-order processor, the 3D design achieves 36% performance improvement over the 2D design with reasonable thermal control.



Lecture 2: Thursday, 17 July 2008 (15h15-16h15) CO3

Thermal-Aware 3D IC Physical Design and 3D Architecture Exploration
In this talk, I shall give an in-depth discussion of our work on Thermal-Aware 3D IC Physical Design and 3D Architecture Exploration. In the first part of the talk, I shall present a thermal-aware 3D IC physical design system developed at UCLA in the past three years, including fast and efficient thermal modeling, 3D floorplanning, 3D placement, and 3D routing with thermal via planning and insertion. I shall discuss the key algorithms used in our 3D physical design tool and the results achieved by the tool in terms of interconnect reduction, density improvement, and thermal control and optimization. Our 3D physical design flow is being integrated into the IBM 3D design flow.

In the second part of my talk, I shall present our ongoing work on 3D microarchitecture exploration, based on the detailed physical prototyping using our 3D physical design tool and cycle-accurate architecture simulation. We consider both tiling and folding of functional blocks in the 3D implementation, including 3D designs of complex functional blocks using word-line folding and port partitioning. We develop a cube packing engine which can simultaneously optimize physical and architectural design for effective utilization of 3D in terms of performance, area and temperature. Preliminary study shows that for a simple out-of-order processor, the 3D design over 30% performance improvement over the 2D design with reasonable thermal control.


About the speaker:
Jason Cong received his B.S. degree in computer science from Peking University in 1985, his M.S. and Ph. D. degrees in computer science from the University of Illinois at Urbana-Champaign in 1987 and 1990, respectively. Currently, he is a professor and the chairman of the Computer Science Department of University of California, Los Angeles. He is also a co-director of the VLSI CAD Laboratory.

Dr. Cong's research interests include computer-aided design of VLSI circuits and systems, design and synthesis of system-on-a-chip, programmable systems, novel computer architectures, nano-systems, and highly scalable algorithms. He has published over 250 research papers and led over 30 research projects in these areas. Dr. Cong received a number of awards and recognitions, including the Ross J. Martin Award for Excellence in Research from the University of Illinois at Urbana-Champaign in 1989, the NSF Young Investigator Award in 1993, the Northrop Outstanding Junior Faculty Research Award from UCLA in 1993, the ACM/SIGDA Meritorious Service Award in 1998, and the SRC Technical Excellence Award in 2000. He also received four Best Paper Awards selected for the 1995 IEEE Trans. on CAD, the 2005 International Symposium on Physical Design (ISPD), the 2005 ACM Transaction on Design Automation of Electronic Systems, and the 2008 International Symposium on High Performance Computer Architecture (HPCA), respectively. He was elected to an IEEE Fellow in 2000.