Professor
Processor Architecture Laboratory
EPFL, Lausanne, Switzerland

 

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Syntax-Guided Synthesis for Accurate RTL Error Localization and Correction

Thursday, 10 December 2015 at 16:20 in room BC 420

 

Abstract:

Functional verification occupies a significant amount of the digital circuit design cycle. We present a novel approach to improve circuit debugging which not only localizes errors with high confidence, but can also provide semantically-meaningful source code corrections. Our method, which we call FudgeFactor, starts with a buggy design, at least one failing and several correct test vectors, and a list of suspect bug locations. We obtain the suspect locations from a state-of-the-art debugging tool that includes a significant number of false positives. Using this list and a library of rules empirically characterizing typical source code mistakes, we instrument the buggy design to allow each potential error location to either be left unchanged, or replaced with a set of possible corrections. FudgeFactor then combines the instrumented design with the test vectors and solves a 2QBF-SAT problem to find the minimum number of source-level changes from the original code which correct the bug. Our benchmarks demonstrate that our method is able to correct a sizable portion of realistic bugs within a reasonable computational time. With the aid of available golden reference designs, we show that those corrections are, at least on these benchmarks, always valid, non-trivial fixes. We believe that our technique significantly improves upon other debugging tools in two respects: When we succeed, we obtain a much more precise bug localization with no false positives and little or no ambiguity. Additionally, we offer bug corrections that are inherently meaningful and enable designers to quickly recognize and understand the root cause of the bug with a high level of confidence.

About the speaker:

Paolo Ienne is a Professor at the EPFL since 2000 and heads the Processor Architecture Laboratory (LAP). Prior to that, from 1990 to 1991, he was a undergraduate researcher with Brunel University, Uxbridge, U.K. From 1992 to 1996, he was a Research Assistant at the Microcomputing Laboratory (LAMI) and at the MANTRA Center for Neuro-Mimetic Systems of the EPFL. In December 1996, he joined the Semiconductors Group of Siemens AG, Munich, Germany (which later became Infineon Technologies AG). After working on datapath generation tools, he became Head of the embedded memory unit in the Design Libraries division.

His research interests include various aspects of computer and processor architecture, reconfigurable computing, on-chip networks and multiprocessor systems-on-chip, and computer arithmetic.
Dr. Ienne was a recipient of Best Paper Awards at the 40th Design Automation Conference in 2003 and at the International Conference on Compilers, Architectures, and Synthesis for Embedded Systems in 2007. He is or has been a member of the program committees of several international workshops and conferences, including Design Automation and Test in Europe (DATE), the International Conference on Computer Aided Design (ICCAD), the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), the International Symposium on High-Performance Computer Architecture (HPCA), the ACM International Conference on Supercomputing (ICS), the International Conference on Field Programmable Logic and Applications (FPL), and the IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC).