CMOS compatible 3D integrated memristive memory array

Professor
Microelectronic Systems Laboratory
Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland
 

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Thursday, 28 September 2017 at 14:20 in room BC 420

Abstract:

Resistive RAM (ReRAM) elements based on transition-metal oxide layers are rapidly becoming viable options for nonvolatile information storage and for neuromorphic operations, allowing easy integration with conventional CMOS technologies. In this talk, we will review the ongoing research at EPFL on the realization of various ReRAM elements based on TiOx, TaOx, WOx and HfOx layers tailored for low voltage operation, as well as the design and co-integration of the CMOS peripheral circuitry for the read/write operations. In particular, the chip embedding platform enabling post-processing of diced samples for fabrication of memristive elements will be discussed, and examples will be provided for potential neuromorphic functions such as spike-timing-dependent-plasticity (STDP) and back-propagation implemented on cross-bar arrays.

 

About the speaker:

Yusuf Leblebici received his B.Sc. and M.Sc. degrees in electrical engineering from Istanbul Technical University, in 1984 and in 1986, respectively, and his Ph.D. degree in electrical and computer engineering from the University of Illinois at Urbana-Champaign (UIUC) in 1990. Between 1991 and 2001, he worked as a faculty member at UIUC, at Istanbul Technical University, and at Worcester Polytechnic Institute (WPI). In 2000-2001, he also served as the Microelectronics Program Coordinator at Sabanci University.

Since 2002, Dr. Leblebici has been a Chair Professor at the Swiss Federal Institute of Technology in Lausanne (EPFL), and director of Microelectronic Systems Laboratory. His research interests include design of high-speed CMOS digital and mixed-signal integrated circuits, computer-aided design of VLSI systems, intelligent sensor interfaces, modeling and simulation of semiconductor devices, and VLSI reliability analysis.

He is the coauthor of 4 textbooks, namely, Hot-Carrier Reliability of MOS VLSI Circuits (Kluwer Academic Publishers, 1993), CMOS Digital Integrated Circuits: Analysis and Design (McGraw Hill, 1st Edition 1996, 2nd Edition 1998, 3rd Edition 2002), CMOS Multichannel Single-Chip Receivers for Multi-Gigabit Optical Data Communications (Springer, 2007) and Fundamentals of High Frequency CMOS Analog Integrated Circuits (Cambridge University Press, 2009), as well as more than 200 articles published in various journals and conferences.

He has served as an Associate Editor of IEEE Transactions on Circuits and Systems (II), and IEEE Transactions on Very Large Scale Integrated (VLSI) Systems. He has also served as the general co-chair of the 2006 European Solid-State Circuits Conference, and the 2006 European Solid State Device Research Conference (ESSCIRC/ESSDERC). He is a Fellow of IEEE and has been elected as Distinguished Lecturer of the IEEE Circuits and Systems Society for 2010-2011.