Fast HW/SW FPGA-Based Thermal Emulation Framework for Multi-Processor System-on-Chip (MPSoC)

David Atienza, david.atienza@epfl.ch

MPSoCs have been proposed as a promising solution for embedded system design, but the temperature rise on the die in future technologies is a very complex new design challenge. Thermal effects can only be verified in the last phases of the design process, when the final components are available, which can produce large overheads in the production process due to cores and overall MPSoC architecture redesigns.

In this presentation we propose a new HW/SW FPGA-based emulation framework that has been developed in the Integrated Systems Laboratory to enable realistic thermal studies as well as power, energy and performance constraints validation in real-time in an early stage of the MPSoC integration process. Our results show that this HW/SW framework provides detailed cycle-accurate reports with speed-ups of three orders of magnitude compared to cycle-accurate MPSoC simulators. Future work in this research line includes development of run-time thermal management strategies for MPSoCs with real-life inputs.