Some implications for logic synthesis from the coming semiconductor technologies

Chief Technology Officer
Synopsys Inc.
Mountain View, California, USA

 

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Keynote - Thursday, 28 September 2017 at 9:10 in room BC 420
 

Abstract:

We will see the introduction of 7, 5, and 4 nm CMOS technologies in the next few years. The transistor structure will evolve, as there will be less fins, and later probably “nano-slabs” will replace fins. The use of EUV, at least for the lower layers of metal interconnect, is also considered almost a certainty.

These new technologies present significant challenges to Logic Synthesis and what has become its increasingly closer companion, Physical Design. Today logic synthesis systems contain significant pieces of Place & Route systems, such as placement and some global routing. The mix will only increase due to many factors.

One fact is that the architecture of the “standard cell” will continue to change. The increase in the number of heights has been accompanied by a reduction in the tracks available for routing, and we will see even lower numbers. It will be mandatory to look at almost “full” placements during synthesis to produce routable designs.

The use of EUV may allow again the possibility of doing routing in two directions at the layers where this is used, as opposed to the single direction approach used now. While further flexibility is welcomed, it has a negative side. The routing rules are much more complex, and so the capability of designing more compact cells may be countered by the need to space them further apart just so routing can be completed. So it is not clear what will be the scheme that wins.

Power densities will affect even more the performance of designs. The need to account for temperature, or at least some correlated metric such as ratios of switching activity over area needs to be incorporated as part of the optimization techniques.

The talk will describe some of these issues and the impact that they will have on the logic synthesis and physical design algorithms. Important development in these two systems will be absolutely necessary so these new semiconductor technologies fully realize their potential on actual designs.

 

About the speaker:

Antun Domic is Synopsys’ newly appointed CTO. As the company’s technical spokesperson, he will focus on aligning our advanced silicon roadmaps, driving our performance/low-power differentiation, and optimizing engineering execution across all business units. He previously served as executive vice president and general manager of the Synopsys Design Group, for which he led the development of the company's implementation and analog/mixed-signal product lines.

Prior to joining Synopsys in 1997, Antun worked at Cadence Design Systems; at the Microprocessor Group of Digital Equipment Corporation in Hudson, Mass.; and at the Massachusetts Institute of Technology (MIT) Lincoln Laboratories in Lexington, Mass. Dr. Domic holds a BS from the University of Chile in Santiago and a PhD in Mathematics from MIT.