Position statement:

Heterogeneous microsystems for wearables, where’s the system engineer ?

One of tomorrow’s new market drivers for the electronic industry will be “wearables”, with ultra-miniaturization for paving the way towards unobtrusive personal “guardian angels”. On the contrary to today’s portable systems which are resulting from co-assembly of well-bounded electronic components, wearables will be calling for heterogeneous microsystems consisting of entire sensing, processing, actuating, communicating and energy scavenging technologies and fitting within very few cubic millimeters.

For heterogeneous microsystems, co-integration of a broad panel of micro- nano- bio- and radio- micro-components requires miniaturization approaches to go beyond classical co-assembly approaches, by punching through and sometimes dissolving the respective technology barriers. Cross-domain electronic design will be a must to ensure the required performances in such tiny embodiments, and innovative assembly and manufacturing methods will have to be engineered to ensure low-cost manufacturing at the end of the day.

In practice, today’s R&D activities are pushing innovation at the level of the individual technology bricks with many amazing and promising achievements. On the other hand, today’s first heterogeneous microsystems remain quite below expectations in terms of achieved power, performance and size. This is due to the underestimation of the complexity of system integration, combined with “bottom-up” design and assembly methods, which tend to jeopardize the individual technology performances. Heterogeneous microsystem integration is often the end-wagon, leaving it up to some clever system engineer to collect all bricks and make them work altogether.

A first major challenge is to develop innovative top-down methodologies that will enable efficient micro-system partioning across a broad scope of heterogeneous micro-technologies. Novel tools need to be engineered and made available to the system engineer, not only for stimulating co-design across the respective technology boundaries, but also for accompanying higher level assembly and packaging constraints jointly with the development of individual the technology bricks.

Another key challenge concerns manufacturability in the specific context of wearables, where the heterogeneous microsystems may end up into textiles, skin patches or even implants, thereby adding further system-level constraints such as washability, stretchability, bio-compatibility. Low-cost and reliable microsystem-in-package manufacturing flows will be needed, with innovative design-for-manufacturability tools also to be included into the system engineer’s toolbox.

Scientific excellence is already pouring into nano- bio- and micro- technology R&D, but stimulating innovation at system engineering level should not be forgotten. It will be yet another challenge for the scientific and industrial communities to be able to educate system engineers and invest into next generation system-level tools for mastering the complexity of heterogeneous microsystem integration and generating successful implementation into wearables.
 

About the panel member:

Vincent Peiris is heading the Wireless and Sensing Business Unit of EM Microelectronic in Marin, Switzerland, which he joined very recently in September 2014. His principal activities concern the development and production of low-power and low-voltage wireless ICs and modules for Bluetooth Low Energy and proprietary standards. He was previously with CSEM in Neuchâtel, leading the RF and Analog IC sector since 1999. He started this group and conducted pioneering research in the field of ultra-low-power and low-voltage (1V) RF CMOS transceivers and SoC’s which were successfully transferred to several industries in Switzerland and Europe. He has also been acting as coordinator and scientific manager of several large-scale EU projects dealing with ultra-miniature radio ICs and microsystems for WBAN (EU-FP7 WiserBAN, Wear-a-BAN, BLIM4SME). Before joining CSEM, he was with LeCroy in Geneva since 1996, in charge of high-speed GSps digitizers for digital oscilloscopes. In 1995, he was with MIT as visiting scientist at the Microsystems Technology Laboratory. He graduated from the EPFL in Lausanne, with MSc in 1989 and PhD in 1994, both in Electrical Engineering.