Designing Analog/Mixed-Signal IP beyond the 28nm process technology node

As we are moving beyond the 28nm process technology node we are not just faced with shrinking geometries, but are also transitioning from planar transistor structures to FinFET devices. This is introducing a new set of challenges for analog/mixed-signal IP designers. This talk will discuss the issues and propose solutions based on our experience designing IP for 20nm as well as 14nm FinFET processes.

About the speaker:

Joachim Kunkel joined Synopsys in 1994 and is currently senior vice president and general manager of the Solutions Group. In that capacity, he manages the business units responsible for Synopsys DesignWare® intellectual property (IP), strategic market development and system-level design. Before coming to Synopsys, Mr. Kunkel was co-founder of CADIS GmbH in Aachen, Germany. There, he served as managing director and performed myriad duties in engineering, sales and marketing. Before co-founding CADIS, Mr. Kunkel was a research assistant at the Aachen University of Technology, where he conducted research in system-level simulation techniques for digital signal processing, with special emphasis on parallel computing. Mr. Kunkel holds an MSEE degree, the Dipl.-Ing. der Nachrichtentechnik, from the Aachen University of Technology.