Nanoscale Systems and Technologies

Workshop, 5-7 October 2005, EPFL INF 328

Wednesday, 5 October 2005
17:15 - 18:00 A Case Study of Mobile SoC Architecture Design Based on Transaction-Level Modeling

Eui-Young Chung
Electrical and Electronics Engineering Department, Yonsei University, Seoul , Korea

Thursday, 6 October 2005
14:15 - 15:00 Designing Quantum Devices and Architectures in CMOS

Edoardo Charbon
Quantum Architecture Group (AQUA), Swiss Federal Institute of Technology, Lausanne

15:00 - 15:30   Coffee break
15:30 - 16:15 Thermal-Aware Clock Tree Design

Enrico Macii
Electronic Design Automation Group (EDA), DAUIN, Politecnico di Torino, Italy

16:15 - 17:00 An Outlook of Technology Scaling Beyond Moore's Law

Adrian Ionescu
Electronics Laboratory (LEG 2), Swiss Federal Institute of Technology, Lausanne

Friday, 7 October 2005
9:15 - 10:00 Bio-chip Platforms: Current Milestones and Challenges Ahead

Luca Benini, Carlotta Guiducci
Microelectronics Research Group, (MICREL), DEIS, University of Bologna, Italy

10:00 - 10:30 Complete FPGA-Based Emulation Framework for Multi-Processor System-on-Chip

David Atienza
Integrated Systems Laboratory (LSI), Swiss Federal Institute of Technology, Lausanne

10:30 - 11:00 Coffee break
11:00 - 11:45 Design Challenges in Nanometer-Scale Systems

Yusuf Leblebici
Microelectronic Systems Laboratory (LSM), Swiss Federal Institute of Technology, Lausanne

11:45 - 12:15 Nanostencil Technique and its Applications to Nanoelectronics

Oscar Vazquez
Microsystems Laboratory (LMIS1), Swiss Federal Institute of Technology, Lausanne

12:15 - 14:00 Lunch break
14:00 - Free discussion session