Position statement:

As technology scales the cost of performing complex numerical calculations decreases both in area and power. On the other hand, for purely analog circuits, the area saving of newer technologies often barely compensate the extra fab cost. This has led designers to eliminate analog blocks in a signal processing chain (e.g. the RX or TX path in a wireless transceiver) and to move the digital interface as close as possible to the source/load (e.g. the antenna). Such a system digitization puts more stress on the interface whose performance need to improve (e.g. the number of bits and sampling rate of both ADCs). Furthermore the performance of new ICs keeps increasing driven by the increasing complexity of the system they enable (e.g. extended LTE terminals implementing MiMo and carrier aggregation). The combined effect of these tendencies is that more and more digital circuits are used to assist the operation of analog circuits.

Early examples of digitally assisted analog circuits are back-ground calibrated ADCs (e.g. SAR or Pipeline) and All Digital PLL. More recently, digital calibration/correction has been proposed also for more complicated sub-systems e.g. the complete TX path of a cellular transceiver. This is still done mostly in an open loop way (e.g. pre-distortion). Close loop operation, although more effective, raises many additional problems still to be addressed in a reliable and general fashion.

For this evolution to have a true impact on actual commercial systems significant progress is still required both on the analog and digital side. For the former case there is a need for:
•    more scaling friendly blocks although some are already available  (e.g. passive mixers in a receiver)
•    higher dynamic range blocks (prior to calibration)
•    new sensing and correction technique with low area, noise and power overhead
•    very wide band close loop circuits and techniques

For the latter case the need is for:

•    fast and computationally efficient circuits/algorithms to drive the correction blocks

About the panel member:

Rinaldo Castello graduated from the University of Genova (summa cum laude) in 1977 and received the M.S. and the Ph. D. from the University of California, Berkeley, in 1981 and 1984. From 1983 to 1985 he was Visiting Assistant Professor at the University of California, Berkeley. In 1987 he joined the University of Pavia where he is now a Full Professor. He consulted for ST-Microelectronics, Milan, Italy up to 2005. In 1998 he started a joint research centre between the University of Pavia and ST and was its Scientific Director up to ‘05. He promoted the establishing of several design centre from multinational IC companies in the Pavia area among them Marvell for which he has been consulting from 2005. Rinaldo Castello has been a member of the TPC of the European Solid State Circuit Conference (ESSCIRC) since 1987 and of the International Solid State Circuit Conference (ISSCC) from 1992 to 2004. He was Technical Chairman of ESSCIRC 1991 and General Chairman of ESSCIRC 2002, Associate Editor for Europe of the IEEE Journal of Solid-State Circuits from 1994 to 1996 and Guest Editor of the July 1992 special issue. From 2000 to 2007 he has been Distinguished Lecturer of the IEEE Solid State Circuit Society. Prof Castello was named one of the outstanding contributors for the first 50 and 60 years of ISSCC and a co-recipient of the Best Student Paper Award at the 2005 Symposium on VLSI of the Best Invited Paper Award at the 2011 CICC and of the Best Evening Panel Award at ISSCC 2012. He was one of the two European representatives at the Plenary Distinguished Panel of ISSCC 2013 and the Summer 2014 Issue of the IEEE Solid State Circuit Magazine will be devoted to him. Rinaldo Castello is a Fellow of the IEEE.