Professor
Integrated Systems Laboratory
Digital Circuits and Systems Group
ETHZ, Zurich, Switzerland

 

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Logic Synthesis in the Twilight of Moore’s Law – Near-threshold, Heterogeneous, 3D Design Looking for a New Toolbox

Friday, 11 December 2015 at 9:20 in room BC 420

 

Abstract:

With the slowing down of Moore's Law, we need logic synthesis more than ever to squeeze the last drop of efficiency from maturing CMOS technology and to hide some of the complexity emerging from the increasing fragmentation of technology options. In this talk I will give some examples, taken from our recent design experience, of challenging problems where design automation  and logic synthesis, in  particular, could give a major productivity and quality boost. More in detail, I will discuss logic synthesis challenges that emerge when designing near-threshold, approximate, and heterogeneous (both single-die and die-stacked) circuits.  I will describe how we are arm twisting available tools and I will provide some insight on what the new generation of tools should deliver in the future.

 

About the speaker:

Luca Benini is the chair of Digital Circuits and Systems at ETHZ. He has served as Chief Architect for the Platform2012/STHORM project in STmicroelectronics, Grenoble in the period 2009-2013. He has held visiting and consulting researcher positions at EPFL, IMEC, Hewlett-Packard Laboratories, Stanford University. He is also a Professor at University of Bologna, Italy.

Dr. Benini's research interests are in energy-efficient system design and Multi-Core SoC design. He is also active in the area of energy-efficient smart sensors and sensor networks for biomedical and ambient intelligence applications. In these areas he has coordinated tens of funded projects, including an on-going ERC Advanced Grant on Multi-scale thermal management of Computing Systems.

He has published more than 700 papers in peer-reviewed international journals and conferences, four books and several book chapters (h-index=82 on Google Scholar). He has been General Chair of the IEEE/ACM Symposium on Low Power Electronics, Network on Chip Symposium and Design and Test in Europe Conference. He is associate editor of the IEEE Transactions on Computer-Aided Design and of the ACM Transactions on Embedded Computing Systems. He is a Fellow of the IEEE and a member of the Academia Europaea and has served for two terms as a member of the steering board of the ARTEMISIA European Association on Advanced Research & Technology for Embedded Intelligence and Systems.