Professor
Electrical Engineering and Computer Science Department
University of Michigan, Ann Arbor, Michigan, USA

Scaling Trends of Energy Efficient, Low Voltage Operation

Energy efficiency increases dramatically with reduced supply voltage operation. However, at lower supply voltages both performance and robustness suffer, creating a delicate trade-off challenge. In this presentation we examine this trade-off in light of process scaling and determine the challenges that need to be address to allow energy efficient operation in advanced process nodes.

Performance loss with voltage scaling can be addressed through increased parallelism for throughput oriented computing combined with occasional voltage boosting for single thread performance. However, further challenges arise from robust operation, increased sensitivity to process variation and intermittent faults, all of which worsen with process scaling. We examine these trade-offs and discuss different SRAM design choices (such as 6T /8T bit cells and assist techniques) and their impact on the optimal operating voltage point and compare this with the trade-offs seen for other system components, such as the pipeline and interconnect structures of a processor. We examine how these trade-offs with process scaling and with processor architecture complexity.  Finally, we present how adaptivity, which is becoming a preferred method for addressing process and environmental variations, will both help address these trade-off challenges as well as introduce new challenges at low voltage operation. We conclude by presenting a prototype architecture that incorporates the discussed trade-offs optimizations and operates with high energy efficiency at near-threshold voltage operating conditions.

 

About the Speaker:  

David Blaauw received his B.S. in Physics and Computer Science from Duke University and his Ph.D. in Computer Science from the University of Illinois, Urbana, in 1991. Until August 2001, he worked for Motorola, Inc. in Austin, TX, where he was the manager of the High Performance Design Technology group and won the Motorola Innovation award. Since August 2001, he has been on the faculty at the University of Michigan where he is a Professor.  He has published over 350 papers, received an extensive number of best paper awards and nominations, and holds 35 patents.  His research is has a three fold focus:  He has investigate adaptive computing to reduce margins and improve energy efficiency using a new approach he pioneered called Razor for which he received the Richard Newton GSRC Industrial Impact Award.  He has active research in resilient circuit design for wear out and error prone silicon. His latest work is focused on ultra-low power computing using near-threshold and subthreshold computing for millimeter sensor systems and high performance serve farms. This work recently lead to a processor design with record low power consumption which was selected as one of the years most significant innovations in the MIT Technology Review.  He was general chair of the IEEE International Symposium on Low Power, technical program chair for the ACM/IEEE Design Automation Conference and a member of the IEEE International Solid-State Circuits Conference.