Professor
Institute for Integrated Signal Processing Systems
RWTH Aachen University of Technology, Germany  

Visiting Professor
Integrated Systems Laboratory
Swiss Federal Institute of Technology, Lausanne, Switzerland

ASIP: The (too) long way from academia to product

Application specific processors (ASIP) are becoming main building blocks in heterogeneous many-processor-system on chip for mobile terminals or serve as a single processor in embedded systems.  ASIP´s are a compromise between two conflicting goals: Flexibility (software definable) and energy efficiency of a computational device. ASIP´s have been proposed over 15 years ago and have gone the usual path of evolution from hype (exaggerated claims) to the trough of disillusionment and an increasingly fast acceptance in industry today. The acceptance history of ASIP´s serves well as an example for the slow acceptance of system level design in industry in general.

In the first part of this talk we use the “Processor Designer^TM” tool suite of Synopsys as a case study. We discuss the functionality and the history of the tool suite which begun as a research project at the RWTH Aachen and which was later on commercialized by the start-up LisaTek^TM. The integration of the tool into a system level design environment for virtual prototyping is shown next.

In the second part of the talk we analyze the reasons for the slow acceptance of new design methodologies in the industry. The reasons range from functionality (“wrong tool”), inadequate business model (“IP or design tool”), inadequate marketing to the conservative mindset of most designer (“I can do everything with Verilog and a C-Compiler”). We also discuss the transformation of academic research to a product in the EDA industry. In that respect it is instructive to observe that disruptive technology in the EDA industry has come from academia and from start-ups.  This leads to the question whether this food chain of the past still exists today. We conclude with speculations about possible development of system level design.
 

About the Speaker:

Heinrich Meyr received his M.Sc. and Ph.D. from ETH Zurich, Switzerland. He spent over 12 years in various research and management positions in industry before accepting a professorship in Electrical Engineering at Aachen University of Technology (RWTH Aachen) where he founded the Institute for Integrated Signal Processing Systems. In 2007 he has assumed the rank of emeritus. Presently he is a visiting professor at the LSI lab of the EPFL directed by Professor Giovanni de Micheli.

During the last forty years, Dr. Meyr has worked extensively in the areas of communication theory, digital signal processing and CAD tools for system-level design. He has published numerous IEEE papers and holds many patents. He is a Life -Fellow of the IEEE and has received three IEEE best paper awards.  In 2000, Dr. Meyr was the recipient of the prestigious Vodafone prize for his outstanding contribution in the area of wireless communications.

Dr. Meyr has a dual career as entrepreneur. He has co-founded a number of successful companies. The last company he has co-founded  was LISATek Inc., a company with breakthrough technology to design application specific processors. The company merged with CoWare in February 2003 and was acquired by Synopsys in spring 2010. From 2003 until 2010 Dr. Meyr held the position of Chief Scientific Officer of CoWare.