Vice President
Electronic Design Automation Technologies
IBM Systems and Technology Group
IBM, New York, USA

 

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EDA 3.0: time to refactor logic synthesis

Friday, 11 December 2015 at 11:40 in room BC 420

 

Abstract:

Why does it take about 3 seconds to look up the shortest path from my home to JFK, and does it take a couple of hours to find the critical path in a large chip in an advanced technology? Are the engineers working on Google maps that much smarter than the engineers in the EDA industry or is there something else at work? Do they have access to much more intelligent and faster algorithms than anybody in EDA ever thought of? Do EDA design tools have to handle that much more data on a chip than the data that has been accumulated in maps or is design data that much more dynamic than a fairly static map of roads?

This presentation will take a first step to answering these questions and spawn a discussion on a new way to implement EDA tools and deliver them in integrated design flows to the market.

 

About the speaker:

Leon Stok studied electrical engineering at Eindhoven University of Technology, The Netherlands, where he graduated with honors in 1986. He obtained his PhD degree from Eindhoven University in 1991. He worked at IBM’s Thomas J. Watson Research Center as part of the team that developed BooleDozer, the IBM logic synthesis tool. Subsequently, he managed IBM’s logic synthesis group and initiated the development of the first physical synthesis system: PDS, IBM’s Placement Driven Synthesis tool. From 1999 to 2004, he led all of IBM’s design automation research as the Senior Manager Design Automation at IBM Research. He is currently Vice President, Electronic Design Automation at IBM. He entered the field of Design Automation 25 years ago intrigued by the type of problems being posed by Moore’s law. He has enjoyed working on problems from high-level synthesis to prescriptive layout design and DFM. In these 25 years, he attended most of the Design Automation Conferences, as a presenter of his original work in papers, a reviewer of the state of the art in tutorials or as a panelist to give his opinion on current issues. He served in many roles as a member of the DAC executive committee and as the chair of the 48th DAC. He is a Fellow of the IEEE.