Assistant Professor
Embedded Systems Laboratory, Director
Swiss Fedarl Institute of Technology, Lausanne, Switzerland
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Tuesday, 14 December 2010 (14h30-15h00), EPFL Polydôme

Green Considerations for System-Level Computing Architectures Design

Digital information management is the key enabler for the continuous improvement in productivity and quality of life experienced by our society. This improvement is provided by the ease of use and availability of a rich set of computing devices and services in continuous progress. Unfortunately, the energy cost and carbon footprint of the computing devices and services has become exorbitant. Moreover, current technological and digital service utilization trends result in doubling the energy cost of the computing systems infrastructure and its carbon footprint in less than five years. In an energy-constrained world, this consumption trend is unsustainable and comes at increasingly unacceptable environmental costs. In this talk, I will first describe what is meant by green computing architectures design at system level from and electrical engineering viewpoint and how precisely its consequences can be quantified. Next, I will review energy-efficient computing components and architectures based on multi-core processing technology, dynamic voltage and frequency scaling, and effective cooling mechanisms. Finally, I will describe techniques for improving performance efficiency per consumed Watt on large-scale computing systems (e.g., a data center), including multi-scale dynamic power control, thermal-aware task placement and scheduling, and novel system-level cooling management approaches for global energy optimizations in computing systems.

About the speaker:

David Atienza is currently Professor of EE and Director of the Embedded Systems Laboratory (ESL) at EPFL, Switzerland, and Adjunct Professor at the Computer Architecture and Systems Engineering Department of Complutense University of Madrid (UCM), Spain. He received his MSc and PhD degrees in Computer Science and Engineering from UCM, Spain, and Inter-University Micro-Electronics Center (IMEC), Belgium, in 2001 and 2005, respectively. His research interests focus on design methodologies for low-power embedded systems and high performance Systems-on-Chip (SoC), including new thermal management techniques for 2D and 3D Multi-Processor SoCs, design methods and architectures for wireless body sensor networks, dynamic memory management and memory hierarchy optimizations, as well as novel architectures for logic and Network-on-Chip (NoC) interconnects. In these fields, he is co-author of more than 120 publications in prestigious journals and international conferences. He has received a Best Paper Award at the IEEE/IFIP VLSI-SoC 2009 Conference, and two Best Paper Award Nominations at the ICCAD 2006 and DAC 2005 conferences. He is an Associate Editor of IEEE Transactions on CAD (in the area of System-Level Design), IEEE Letters on Embedded Systems and Elsevier Integration: The VLSI Journal. He is also an elected member of the Executive Committee of the IEEE Council of Electronic Design Automation (CEDA) since 2008 and a GOLD member of the Board of Governors of IEEE Circuits and Systems Society (CASS) since 2010.