Executive Vice President
Design Enablement & Services
ST Microelectronics, Geneva, Switzerland

 

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A Brief History of FD-SOI : A Faster, Cooler, Simpler Alternative Technology for IoT, Mobile and Servers*

Electronics is ever more pervasive in everyday life: smartphones, connected cars, wearables, Internet of Things… Semiconductor technology is the key enabler of these applications, making possible the impossible by enabling device miniaturization and integration. With the exponential growth of independent but connected objects, a key technology enabler is energy efficient computing, to enable accomplishing tasks with orders-of-magnitude less energy consumption.

UTBB FD-SOI (Ultra Thin Body and Buried-oxide Fully Depleted Silicon On Insulator or FD-SOI) is a planar semiconductor technology that introduces the advantages of fully depleted transistors at the 28nm node (which is cost optimal) enabling both the advantages of a general purpose high speed technology together with that of a low power technology.

This keynote will present the 20-year history of the collaborative development of the FD-SOI technology and its main characteristics, especially suited for highly energy efficient operation (and outstanding at ultra-low voltage conditions). FD-SOI is not only optimal for back-biasing digital logic but also best-in-class for memory bit-cells variability and provides exceptional analog/RF characteristics. The FD-SOI application domains therefore include wearables, mobile, but also networking and micro-servers. We will illustrate the advantages offered by the FD-SOI technology in these various contexts, and demonstrate how that technology can enable new and innovative applications in these domains, as well as specific advantages for Automotive systems.

Philippe Magarshack is Executive Vice President of STMicroelectronics in charge of Design Enablement & Services. He has had these responsibilities since March 2012.

From 1985 to 1989, Magarshack worked as a microprocessor designer at AT&T Bell Labs in the USA. In 1989, he joined Thomson-CSF in Grenoble, France, and took responsibility for libraries and ASIC design kits for the military market. In 1994, Magarshack joined the Central R&D Group of SGS-THOMSON Microelectronics (now STMicroelectronics), where he has held several roles in CAD and Libraries management for advanced integrated-circuit manufacturing processes. In 2005, Magarshack was promoted to Group Vice President and General Manager of Central CAD and Design Solutions at STMicroelectronics’ Technology R&D and Manufacturing organization.

Magarshack is ST’s Enablement Executive at the IBM ISDA Technology Alliance for the development of advanced CMOS process. He sits on the boards of Silicon Integration Initiative (Si2) and ENSIMAG Engineering School in Grenoble.

Philippe Magarshack was born in London, UK, in 1961. He graduated with an engineering degree in Physics from Ecole Polytechnique, Palaiseau, France, and with an Electronics Engineering degree from Ecole Nationale Supérieure des Télécommunications in Paris, France.

 

* Due to a last minute change in Phillipe Magarshack's schedule, this talk will be given by Giorgio Cesana.

About the speaker:

Giorgio Cesana is Director of Marketing and Communication at the Technology R&D Group of STMicroelectronics (ST). He joined ST's Central R&D in Agrate, Italy in 1994, then moving to Crolles, France, in 2000. In 2009, he created the activity of Technology R&D Marketing. In this role, he determines market demand for future technology and design platforms, oversees dedicated technology developments, monitors industry trends in new technologies and provides PPA benchmarks. Currently, he is in charge of the marketing definition of the FD-SOI technologies of STMicroelectronics.