Scientist, Implementation Group
Synopsys Inc.
Mountain View, California, USA

Static Timing for the Other 99%

Static timing analysis (STA) is a cornerstone for design and verification of today’s SoC’s. The challenges of building larger systems with more complex constraints and much smaller geometries have introduced new complexities that force us to rethink approaches. For example, embedded memories with their complex but critical timing signals are quickly dominating silicon real-estate, but have largely been ignored by the STA world until recently. In another example, while gate-level STA approaches are almost universally accepted, some main-stream design groups are now including transistor-level STA as part of the flow to handle more complex design styles, reduce pessimism, and address nanometer effects at a deeper level. The talk will examine limitations that are becoming more relevant with shrinking geometries and will examine new approaches being explored to address the challenges of modern IC design.

 

About the Speaker:

Larry G. Jones received his Ph.D. from The Pennsylvania State University in 1986. He was an Assistant Professor of Computer Science at the University of Illinois Urbana-Champaign from 1986 to 1992. From 1992 to 2000, he held senior management roles at Motorola, including Director of the Moscow Research Laboratory and Managing Director of the Phoenix Software Center.  From 2000 to 2001, Dr. Jones served as Vice President of Engineering at Cadabra Design Automation. Joining Synopsys in 2001, Dr. Jones is a Synopsys Scientist and chief architect of transistor-level static timing products.