Netchip: A complete tool flow for Networks on Chips (NoC) Design

Srinivasan Murali, srinivasan.murali@epfl.ch

With technology scaling, the number of processor/memory cores in Systems on Chips is rapidly increasing. To tackle the increasing communicational complexity of the design, scalable Networks on Chips (NoC) are needed.

To manage the huge design complexity of NoCs, it is important to provide efficient CAD tool support to automate the most time-intensive design steps.  In this project, we present a complete tool flow to perform efficient NoC topology design, application mapping, RTL simulation/synthesis model generation and integration of the models with the traditional physical design process. Using the flow, we could design the NoC for a multi-media application from input specifications to layout in a few hours, a process that usually takes several weeks.