Associate Professor
Tokyo Institute of Technology, Tokyo, Japan

Lecture 1: Wednesday, 16 July 2008 (10h00-11h00) CO3

Classical versus Ballistic Transports
The physical gate length of modern, advanced MOSFETs is well less than 30 nm, and it is expected that the gate length will be less than 10 nm in 2016. In such short channel devices, charged carriers, which flow in MOS devices, will have less scattering events from source to drain. If no scattering occurs, this situation is called "ballistic transport". Whereas, in classical long channel devices, scattering events are frequent, and thus the carrier transport are strongly restricted by these events. Therefore, ballistic transport, namely no scattering, is an ideal situation for the carrier transport in advanced MOSFETs. In this talk, the relationship between classical and ballistic transports will be firstly shown. Then, the strategy to enhance current even in ballistic regime will be discussed.



Lecture 2: Thursday, 17 July 2008 (11h15-12h15) CO3

Performance Booster technologies for advanced MOSFETs: Stress Engineering and Surface Orientations other than (001)
The performance of MOSFETs have been improved by shrinking their dimensions. However, in recent years, the scaling of device sizes has less impact on the performance enhancement. Whereas, it has been realized that the enhancement of low-field mobility contributes to boost the MOSFET performance. Therefore, mobility booster technologies such as stress engineering and the utilization of surface orientations other than (001) have been attracting much attention. In this talk, stress engineering for higher-performance MOSFETs will be firstly introduced. Physical mechanisms for the electron/hole mobility enhancement by stress will be discussed, and then the optimum stress directions for higher-performance MOSFETs will be shown. Finally, the impact of surface orientation change on MOSFET characteristics will be reviewed. Particularity, electron/hole transport in (011) MOSFETs will be extensively discussed.



About the speaker:

Ken Uchida received B.S. degree in physics, M.S. and Ph.D. degrees in applied physics all from the University of Tokyo, Tokyo, Japan, in 1993, 1995, and 2002, respectively. In 1995, he joined the Research and Development Center, Toshiba Corporation, Kawasaki, Japan. He has studied carrier transport in nanoscale devices such as Single-Electron Devices, Schottky source/drain MOSFETs, Ultrathin-body SOI MOSFETs, Strained Silicon MOSFETs, Carbon Nanotube Transistors, and (110) Si MOSFETs.

Dr. Uchida is a member of the Japan Society of Applied Physics and IEEE Electron Devices Society. He won the 2003 IEEE EDS Paul Rappaport Award for his work on single-electron devices and 2005 Young Scientist Award from Ministry of Education, Culture, Sports, Science and Technology of Japan. He served as a subcommittee member (2005, 2006) as well as the subcommittee chair (2007) of Solid-State & Nanoelectronic Devices (SSN) subcommittee of IEEE International Electron Devices Meeting (IEDM). He was a program committee member of IEEE Silicon Nanoelectronics Workshop (SNW) in 2003, 2005, 2006, and 2007. He is a Distinguished Lecturer of IEEE Solid-State Circuit Society (SSCS) in 2007 and 2008.