Walter Weber, Namlab, Dresden, Germany

A promising perspective for the advancement of electronics beyond Moore´s law is given by the extension of functional diversity per computing unit. Reconfigurable field effect transistors (RFETs) are such novel multifunctional devices that provide n- and p- FET characteristics as selected by an electric signal. Future computing circuits can make use of this reconfiguration method to perform different logic operations with the same hardware. We will show the working principle and characteristics of a 4 terminal RFET based on the individual gating of two reversed Schottky junctions integrated as metal/ Si / metal nanowire heterostructures. Scanning gate microscopy was applied to provide experimental evidence of the dominant electronic transport mechanisms in these nano-structures and to validate the use of individual junction gating amongst various concept realizations. The electric characteristics of optimized devices will be shown and analyzed with device simulations. Different RFET realization concepts will be compared at the device level. Moreover, the current device challenges and prospects for the device improvement towards circuit implementation will be discussed.

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Michele De Marchi, EPFL, Lausanne, Switzerland

We present new ambipolar silicon nanowire (SiNW) FET transistors with in-field polarity control, featuring two independent gate-all-around electrodes and vertically stacked SiNW channels. In our device, one gate electrode enables dynamic configuration of the device polarity (n or p-type), while the other switches on/off the device. Measurement results on silicon show I_on/I_off > 10⁶ and S ≈ 64mV/dec (70mV/dec) for p(n)-type operation in the same device. Our top-down fabrication presents a straightforward approach with great potential in terms of scalability, large-scale integration and compatibility with current CMOS fabrication processes. We show that XOR operation is embedded in the device characteristic, and we demonstrate for the first time a fully functional 2-transistor XOR gate.

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Andras Kis, EPFL, Lausanne, Switzerland

Two-dimensional crystals offer several inherent advantages over conventional 3D electronic materials or 1D nanomaterials such as nanotubes and nanowires. Their planar geometry makes it easier to fabricate circuits and complex structures by tailoring 2D layers into desired shapes. Because of their atomic scale thickness, 2D materials also represent the ultimate limit of miniaturization in the vertical dimension and allow the fabrication of shorter transistors due to enhanced electrostatic control. Another advantage of 2D semiconductors is that their electronic properties (band gap, mobility, work function) can be tuned for example by changing the number of layers or applying external electric fields. We have recently demonstrated that a 2D material in the form of semiconducting single-layer MoS₂ could be used to fabricate dual-gate field-effect transistors. We have also incorporated MoS₂-based transistors into simple functional circuits and used them as inverters and analogue amplifiers.

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Shu Nakaharai, AIST, Japan

We present the device operations of novel dual-gated graphene transistors in which the transistor polarity (n or p) is electrostatically reversible by the gate bias of one of the top gates. In the new device, a channel is defined as the region between a pair of top gates, where graphene is irradiated by accelerated helium ion beam to form defect-induced transport gap. The polarity of carriers in top-gated graphene regions on both sides of the channel is controlled by the top gates to form a gate-controlled p-i-n junction, and the device will be on state when it is in p-i-p or n-i-n configurations and off state when in p-i-n or n-i-p configurations. This novel concept device enables unipolar graphene transistors, while graphene itself is intrinsically ambipolar. Based on this new device concept, we demonstrate unipolar transistor operations in both nFET and pFET modes in an identical device with the maximum on-off ratio larger than three orders of magnitude at 200 K.

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Joachim Knoch, RWTH Aachen, Germany

One-dimensional semiconducting nanostructures have recently attracted a great deal of interest for nanoelectronics devices. In particular, carbon-based nanostructures such as carbon nanotubes of nanoribbons seem to be ideally suited for ultimately scaled field-effect transistors due to their small size and excellent electronic transport properties. It has been shown that one-dimensional electronic transport is beneficial not only for conventional FETs but also for novel device concepts such as band-to-band tunneling field-effect transistors. However, doping these nanostructures appropriately is a delicate task. Here we will present recent experimental and theoretical work on employing additional gates to create appropriate doping profiles in carbon nanotube FETs.

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Max Shulaker, Stanford University, California, USA

Low-power applications, such as sensing, are becoming increasingly important and demanding in terms of minimizing energy consumption, driving the search for new and innovative interface architectures and technologies. Carbon Nanotube FETs (CNFETs) are excellent candidates for further energy reduction, as CNFET-based digital circuits are projected to potentially achieve an order of magnitude improvement in energy-delay product at highly scaled technology nodes. We present the first demonstration of a complete sensor interface circuit implemented entirely using CNFETs. We demonstrate our CNFET sensor interface by using the CNFET circuitry to interface with a sensor used to control a handshaking robot.

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Gianluca Piccinini*, Politecnico di Torino, Torino, Italy

The model presented is a charge-based model that assures the continuity of the current and the analytical derivability of charges to obtain the parasitic capacitances. It has been conceived to support the multiple independent gates, typical of nano-array structures, where each gate controls the charge in the channel. Charge conservation implies constant current in the different section of the multiple gate nanowire FET, making possible the development of a compact model for an arbitrary number of gates. The model has been used to describe different structures (i.e. number of gates, dimension of the single transistor and ranges of applied voltages) under static conditions and the results have been verified on Silvaco TCAD simulations. The modeling approach and the attained results for some cases of study will be presented and discussed.

*This presentation was delivered by Stephano Frache.

Ian O'Connor, Institute of Nanotechnologies of Lyon, Ecully, France

Ambipolar double gate field effect transistors (ADG-FETs) enable the development of completely new logic circuit structures and design paradigms. Conventional logic synthesis techniques cannot represent the capability of ADG-FETs to operate as either n-type or p-type switches and new techniques must be found to build optimal logic. This talk will discuss some design techniques to enable the synthesis of logic cells based on such devices by defining generic approaches and design techniques based on ADG-FETs. Two different contexts are tackled: (i) improving standard cell logic design with more compact structures and better performance, as well as low-power design techniques exploiting the fourth terminal of the device, and (ii) adapting conventional logic synthesis techniques such as Binary Decision Diagrams or Function Classification to ADG-FETs in order to build reconfigurable logic cells.

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Haykel Ben Jamaa*, CEA, LETI, Minatec Campus, Grenoble, France

Several novel devices show an ambipolar behavior, which is characteristic of intrinsic channel materials, gate stack and drain/source engineering. The ambipolarity can be cancelled by means of technology techniques, or it can be controlled by means of a back gate. An optimal engineering of the second gate results in two-input device that implements binate functions in a compact and smart way. In this talk, we will show physical design aspects that leverage the utilization of binate logic gates. We will introduce a new library of logic cells based on controllable ambipolar logic gates. Then, we will assess their impact on the circuit level by synthesizing a large set of logic functions. We will focus on the FPGA design and show that the considered devices are suitable not only from the physical point of view, but they also yield more compact circuits with a higher performance.

* This presentation was delivered by Pierre-Emmanuel Gaillardon.

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Shashi  Bobba, EPFL, Lausanne, Switzerland

As we advance into the era of nanotechnology, semiconductor devices are scaled down to their physical limits. In this nanometer regime, most devices inherently exhibit ambipolar behavior. New design methodologies are proposed for exploiting the phenomenon of controllable polarity. Technology based on Silicon nanowires field-effect transistors (SiNWFET) is promising due to its top-down Si-CMOS compatible process design flow. A double-gate ambipolar SiNWFET operates as p-type or n-type by electrically controlling the polarity of the second gate. In this talk, I will present layout techniques to address gate-level routing congestion for double-gate SiNWFET, as every transistor has two gates to route. Novel symbolic layouts, which are technology independent, are proposed for ambipolar circuits. In the second part of this talk, I will present an approach for designing an efficient regular layout, called Sea-of-Tiles (SoTs). By mapping various circuit benchmarks on to the SoT fabric an optimum tile is determined.

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Fabien Clermidy, CEA, LETI, Minatec Campus, Grenoble, France

Using ambipolarity features of DG-CNTFET can help obtaining a very dense reconfigurable cell based on few transistors. However, high density of interconnects around the cells in actual Field-Programmable-Gate Arrays (FPGA) completely remove the interest of these ultra-dense cells. This problem imposes to revisit the architecture of FPGA in order to find a more balanced interconnect/logic proportion. In this talk, we propose a hierarchical architectures mixing programmable and fixed interconnects. We then show the potential gain depending on the modularity of the fixed interconnect part considering function mapping.

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Luca Amaru, EPFL, Lausanne, Switzerland

Controllable polarity is a profitable feature demonstrated in Double-Gate (DG) transistors based on Silicon NanoWires (SiNWs), carbon nanotubes and graphene. Thanks to the on-line configuration of the n- or p-type polarity via the second gate, such emerging devices enable compact realizations for functions embedding the biconditional (XNOR) logical connective. In this talk, we first present Biconditional Binary Decision Diagram (BBDD): A novel canonical BDD where the Shannon's expansion is replaced by the biconditional expansion. Then, we propose a direct mapping scheme of controllable polarity devices onto BBDD structures. Experimental results show that the proposed method reduces the DG controllable polarity FETs count by 49.7% on average compared to commercial logic synthesis tool.

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Sébastien Le Beux, Institute of Nanotechnologies of Lyon, Ecully, France

Among the key issues facing the semiconductor industry as increasingly unreliable emerging and nanoscale technologies come to the fore are design reliability and manufacturing yield. In this talk, we present a fault-tolerant architecture based on Carbon Nanotube Field-Effect-Transistors (CNTFET). The architecture is composed of statically interconnected reconfigurable cells. Static interconnects offer possibilities for scalable and low power circuits while cell reconfiguration is extensively used to increase the architecture fault-tolerance. We show that in the proposed architecture, for a 96% carbon nanotube manufacturing yield, up to 83% of the hardware resources can still be used.

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