Nanoelectronic Circuits and Tools

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This five-day Summer School brings together instructors from renowned universities and research centres around the world with morning sessions dedicated to Nanoscale Electronics and afternoon sessions to Computer Aided Design. Don't miss this exciting opportunity!

Registration is required to attend lectures. Registration fee is 150 CHF and includes daily lunch at an on-campus restaurant and all coffee breaks during the week of the summer school. All lectures will take place in Auditorium C03. Lecture abstracts can be reached by clicking on the highlighted lecturer name below.

Important notice:
Please note that the summer school lectures can be taken by all interested EPFL PhD students, for doctoral course credit (full attendance and term paper required).

Download schedule (729 KB pdf).

Download EPFL map (1.1 MB pdf)

Morning session: Nanoscale Electronics (10:00 - 12:15)
Date: Lecturer: Schedule:
Monday
14 July 		H.-S. Philip Wong
Stanford University 		10:00-11:00 Beyond CMOS Scaling - What's Next?
11:00-11:15 Coffee break
11:15-12:15 The Future of CMOS Scaling
Tuesday
15 July 		Shunri Oda
Tokyo Institute of Technology 		10:00-11:00 Silicon quantum dots: the future of electronics and photonics?
11:00-11:15 Coffee break
11:15-12:15 Novel Nano-ElectroMechanical-System Devices
Wednesday
16 July 		Ken Uchida
Tokyo Institute of Technology 		10:00-11:00 Classical versus Ballistic Transports
11:00-11:15 Coffee break
11:15-12:15 Performance Booster Technologies for Advanced MOSFETs: Stress Engineering and Surface Orientations other than (001)
Thursday
17 July 		Kaustav Banerjee
UC Santa Barbara 		10:00-11:00 Carbon Nanotube Interconnects for Next Generation ICs- Part I
11:00-11:15 Coffee break
11:15-12:15 Carbon Nanotube Interconnects for Next Generation ICs- Part II
Friday
18 July 		Gianfranco Cerofolini
University of Milano-Bicocca 		10:00-11:00 Silicon in vivo - Linking the world of microelectronics to that of living systems
11:00-11:15 Coffee break
11:15-12:15 A roadmap to nanobio-sensing
Afternoon session: Computer Aided Design (14:00 - 16:15)
Date: Lecturer: Schedule:
Monday
14 July 		Dennis Sylvester
University of Michigan 		14:00-15:00 Pushing Nanoscale CMOS: Design-related Challenges
15:00-15:15 Coffee break
15:15-16:15 Extending Nanoscale CMOS: Analyze, Sense, Correct, and Exploit
Tuesday
15 July 		Massoud Pedram
University of Southern California 		14:00-15:00 Minimizing Leakage Power in CMOS: Technology Issues
15:00-15:15 Coffee break
15:15-16:15 Minimizing Leakage Power in CMOS: Design Optimization Techniques
Wednesday
16 July 		Jason Cong
UCLA 		14:00-15:00 Design for Nanotechnologies and 3D ICs
15:00-15:15 Coffee break
15:15-16:15 Thermal-Aware 3D IC Physical Design and 3D Architecture Exploration
Thursday

17 July

 Subhasish Mitra
Stanford University 		14:00-15:00 Carbon Nanotube Transistor Circuits: Opportunities, Challenges, and Experimental Demonstration
15:00-15:15 Coffee break
15:15-16:15 Imperfection-Immune Carbon Nanotube VLSI Logic Circuits
Friday
18 July 		Pol Marchal
IMEC 		14:00-15:00 A road map for 3D Technologies and their Design Opportunities
15:00-15:15 Coffee break
15:15-16:15 Path Finding - a design/ technology co-exploration