Bringing technology information into early steps of logic synthesis

Associate Professor
Institute of Informatics
Universidade Federal do Rio Grande do Sul (UFRGS)
Porto Alegre, RS, Brazil

 

Webpage

Friday, 29 September 2017 at 14:40 in room BC 420

Abstract:

Logic synthesis most powerful transformations occur at early steps, that abstract target technology information. At the same time, most design costs are caused by technology issues. In this talk we discuss how to bring technology information into early steps of design flow. Our proposal is based on some enablers, including: (1) Use of placed AIGs, with explicit inverters, (2) Using KL-cuts as a tool for logic aware partitioning, (3) Treating logic computation and logic (signal) distribution distinctly, and (4) relying on global timing budget expressed through local design constraints (SDC files). Based on these enablers we describe a new design flow, that has novel design problems aiming at seamless introducing technology information throughout the low, starting at early steps.

About the speaker:

André Reis is a Professor at the Institute of Informatics, UFRGS, Brazil, since 2000. He is a senior member of IEEE and ACM, and published more than 200 academic papers and he has also 10 granted USA patents. He received best paper awards from IFIP VLSI 1997, SBCCI 2013 and IWLS 2015. Prof. Andre Reis is actively involved with the organization of ACM/IEEE International Workshop on Logic and Synthesis, where he acted in several positions, including general chair (Mountain View, 2015), program chair (Austin, 2016), finance chair (Austin, 2017) and he is a member of the steering committee (2016 to 2020). Andre Reis is an advisor for Nangate Inc since 2005, and coordinated cooperation directly between UFRGS and Nangate, as well as among Nangate,UFRGS and other six european partners (Nangate, UFRGS, IMEC, Thales, ST Microelectronics, UPC, Polimi and Leading Edge) during the european FP7project Synaptic. Andre Reis is interested in EDA, with special interests in 1) mixing logic and physical synthesis to improve the overall design flow, (2) using general purpose optimization solvers (SAT, SMT, ILP), (3) scalability for large designs (through parallelism and EDA 3.0). Additional interests include technical writing, and Prof. Andre Reis teaches a course on scientific writing including articles and patents, having extensive experience with intellectual property legal aspects. Prof. Andre Reis wrote more than 500 poems, including one that was selected for the highly selective Poemas no Onibus (Poetry in Public Transportation) contest promoted by the city of Porto Alegre.