Logic Synthesis and Automation for Memristive Memory Processing Unit

Assistant Professor
Andrew and Erna Viterbi Faculty of Electrical Engineering
Technion - Israel Institute of Technology
Haifa, Israel

Webpage

Thursday, 28 September 2017 at 14:00 in room BC 420

Abstract:

Memristors are capable to both store and process data within the same cells. This capability is the fundamental principle in the design of a memristive Memory Processing Unit (mMPU). The mMPU consists of a memristive memory array and a controller that supports memory and processing operations. For processing, the controller produces a sequence of basic logical operations that can be performed within the memristive memory array. In this talk, SIMPLE, a framework that optimizes the execution of an arbitrary logic function within an mMPU, while considering all the constraints involved in performing it within a memristive memory will be explained. SIMPLE automatically generates a defined sequence of atomic Memristive Aided Logic (MAGIC) NOR operations, whose implementation can be facilitated efficiently within the memory. Motivated to overcome the memory-CPU bottleneck, this approach designs an optimal solution in terms of performance by exploiting the parallelism of the MAGIC NOR gates. SIMPLE achieves performance speedups of 2X compared to a previous work and 1.5X compared to a naïve optimization based on standard synthesis tools.

 

 

About the speaker:

Shahar Kvatinsky is an assistant professor at the Andrew and Erna Viterbi Faculty of Electrical Engineering, Technion – Israel Institute of Technology. He received the B.Sc. degree in computer engineering and applied physics and an MBA degree in 2009 and 2010, respectively, both from the Hebrew University of Jerusalem, and the Ph.D. degree in electrical engineering from the Technion – Israel Institute of Technology in 2014. From 2006 to 2009 he was with Intel as a circuit designer and was a post-doctoral research fellow at Stanford University from 2014 to 2015. Kvatinsky is an editor in Microelectronics Journal and has been the recipient of the 2015 IEEE Guillemin-Cauer Best Paper Award, 2015 Best Paper of Computer Architecture Letters, Viterbi Fellowship, Jacobs Fellowship, ERC starting grant, the 2017 Pazy Memorial Award, the 2014 and 2017 Hershel Rich Technion Innovation Awards, 2013 Sanford Kaplan Prize for Creative Management in High Tech, 2010 Benin prize, and six Technion excellence teaching awards. His current research is focused on circuits and architectures with emerging memory technologies and design of energy efficient architectures.