Advances in Industrial Logic Synthesis

Senior II R&D Engineer
Design Group, Synopsys Inc.
Mountain View, California, USA
 

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Thursday, 28 September 2017 at 11:20 in room BC 420

Abstract:

Logic synthesis is a key design step which optimizes abstract circuit representations and links them to technology. In this talk, we present recent innovations in industrial logic synthesis, with a focus on data structures and algorithms for optimization. First, we tackle fundamental challenges in exact delay synthesis. Then, we improve the efficiency of Boolean resynthesis engines. We evaluate the impact of both innovations, and show sensible gains in quality-of-results, over industrial benchmarks, at small runtime cost. These results confirm the continuing importance of logic optimization and synthesis in EDA, and exhibit room for improvements in other logic applications.

About the speaker:

Luca Amaru is Senior II R&D Engineer in the Design Group of Synopsys Inc., Mountain View, CA, USA. He is responsible for designing efficient data structures and algorithms for logic synthesis tools.
Previously, he was research assistant at EPFL, Integrated Systems Laboratory, Lausanne, Switzerland (2011-2015), and visiting researcher at Stanford University, Palo Alto, CA, USA (2014).
Dr. Amaru received his PhD degree in Computer Science from EPFL, Lausanne, Switzerland (2015). He received his double Master's Degree in Electronic Engineering, with honors, from Politecnico di Torino, Turin, Italy, and Politecnico di Milano, Milan, Italy (2011). He received his Bachelor's Degree in Electronic Engineering, with honors, from Politecnico di Torino, Turin, Italy (2009).
At present, Dr. Amaru is author or coauthor of 70 scientific articles and inventor or coinventor of 8 patents