Go to
Lionel Torres
Embedded Hardware and IoT Security
We experience regularly Digital Rights Management technologies downloading Smartphone Apps from AppStores, MP3s or movies from iTunes and eBooks from Amazon. It can also be when using streaming services such as Deezer, Spotify or Netflix. These access control technologies intend to ensure the legitimate use of digital contents after sale.
In the semiconductor industry, DRM technologies such as FlexLM and RLM are commonly used by EDA vendors to control the usage of their design tools and their revenue. In particular, they operated, from mid-90, a significant business model switch to prefer time-based licenses over original perpetual licenses for a better revenue stability over long term.
We propose here how it is possible to deliver soft IPs to build an on-chip hardware infrastructure enabling a secure licensing of hardware component instances, per manufactured chip. This mechanism can help IoT market to enhance security of smart connected objects.
The chip identity can possibly be implemented with a Physical Unclonable Function (PUF) delivering a unique ID for a given manufactured chip.
In addition, different sensor authenticator types are needed to build an overall solution :
- DNA primitives
- Third party PUF provider solutions
- Any secured and trusted key loaded on each unit chip.
In this way the license is generated for each chip based on its ID. Multiple instrumented IPs from different vendors at different levels of hierarchy can be connected with one DRM Controller and one authenticated Sensor.
At design phase, designer simply needs to insert a DRM controller, which is fully compatible with traditional digital design and verification methodologies. Once the chip is manufactured or the FPGA programmed, each distinct physical instance requires a unique runtime license key to activate the functions protected with a secured license protocol. Even though thousands or millions of identical devices are produced, each one of them requires a unique license key to control its activation at operational runtime. In this way we can imagine to propose a secure IP able to be activated or not depending of the application context or environment. This DRM solution allows designing once, but activating every single hardware device.
This work has been carried out with the Algodone company (www.algodone.com)
About the panel speaker:
Lionel Torres obtained respectively his Master and PhD degree in 1993 and 1996 from the University of Montpellier. From 1996 to 1997 he was in ATMEL company as IP core methodology R&D engineer. From 1997 to 2004 he was assistant professor at the University of Montpellier, Polytech Montpellier engineering school (Microelectronic design) and LIRMM laboratory. Since 2004 he is full Professor and was at the head of the Microelectronic dpt of the LIRMM from 2007 to 2010. He is now deputy head of Polytech Montpellier (engineering school of Montpellier) in charge of research, international and industrial relationship. Since 2015 he leads the LABEX (Laboratory of Excellence) for digital and hardware solutions, modelling for the environment and life sciences (budget about 8M€, 65 research project over 170 researchers, and 70 International cooperations).
His research interests and skills concern adaptive VLSI architecture based on emerging technology and Hardware security. He is co-founder of the ALGODONE company, based at Montpellier, Algodone proposes an innovative technology to control the legitimate use of digital content associated with an IP block or a circuit. Lionel Torres is involved in various major conferences as DATE, VLSI, FPL, ISVLSI, DAC and is (co)author of more than 40 journal papers and 170 conference publications, and around 10 patents. He leads several national, and European projects concerning emerging technologies and Hardware security.
Secondary navigation
- EPFL Workshop on Logic Synthesis and Emerging Technologies
- Luca Amaru
- Luca Benini
- Giovanni De Micheli
- Srini Devadas
- Antun Domic
- Rolf Drechsler
- Pierre-Emmanuel Gaillardon
- Jie-Hong Roland Jiang
- Akash Kumar
- Shahar Kvatinsky
- Yusuf Leblebici
- Shin-ichi Minato
- Alan Mishchenko
- Vijaykrishnan Narayanan
- Ian O'Connor
- Andre Inacio Reis
- Martin Roetteler
- Julien Ryckaert
- Mathias Soeken
- Christof Teuscher
- Zhiru Zhang
- Symposium on Emerging Trends in Computing
- Layout synthesis: A golden DA topic
- EPFL Workshop on Logic Synthesis & Verification
- Luca Amaru
- Luca Benini
- Robert Brayton
- Maciej Ciesielski
- Valentina Ciriani
- Jovanka Ciric-Vujkovic
- Jason Cong
- Jordi Cortadella
- Giovanni De Micheli
- Antun Domic
- Rolf Drechsler
- Henri Fraisse
- Paolo Ienne
- Viktor Kuncak
- Enrico Macii
- Igor Markov
- Steven M. Nowick
- Tsutomu Sasao
- Alena Simalatsar
- Leon Stok
- Dirk Stroobandt
- Tiziano Villa
- Symposium on Emerging Trends in Electronics
- Raul Camposano
- Anantha Chandrakasan
- Jo De Boeck
- Gerhard Fettweis
- Steve Furber
- Philippe Magarshack
- Takayasu Sakurai
- Alberto Sangiovanni-Vincentelli
- Ken Shepard
- VENUE
- Panel on Circuits in Emerging Nanotechnologies
- Panel on Emerging Methods of Computing
- Panel on The Role of Universities in the Emerging ICT World
- Panel on Design Challenges Ahead
- Panel on Alternative Use of Silicon
- Nano-Bio Technologies for Lab-on-Chip
- Functionality-Enhanced Devices Workshop
- More Moore: Designing Ultra-Complex System-on-Chips
- Design Technologies for a New Era
- Nanotechnology for Health
- Secure Systems Design
- Surface Treatments and Biochip Sensors
- Security/Privacy of IMDs
- Nanosystem Design and Variability
- Past Events Archive