Professor
Head of the Group for Computer Architecture
Institute of Computer Science
University of Bremen/DFKI, Bremen, Germany

 

Webpage

Using Formal Techniques for Design for Verifiability

Thursday, 10 December 2015 at 14:40 at BC 420

 

Abstract:

In classical circuit design the netlists are first synthesized, while verification is done as a post-processing. Dependent on device under verification (DUV) and the realized functionality, verification may fail. In this talk the question is addressed, whether techniques exist that allow for complete verification in polynomial time and space. Techniques are studied that are based on formal proof engines.
 

About the speaker.

Rolf Drechsler received the Diploma and Dr. Phil. Nat. degrees in computer science from J.W. Goethe University Frankfurt am Main, Frankfurt am Main, Germany, in 1992 and 1995, respectively. He was with the Institute of Computer Science, Albert-Ludwigs University, Freiburg im Breisgau, Germany, from 1995 to 2000, and with the Corporate Technology Department, Siemens AG, Munich, Germany, from 2000 to 2001. Since October 2001, he has been with the University of Bremen, Bremen, Germany, where he is currently a Full Professor and the Head of the Group for Computer Architecture, Institute of Computer Science. In 2011, he additionally became the Director of the Cyber-Physical Systems group at the German Research Center for Artificial Intelligence (DFKI) in Bremen.

His current research interests include the development and design of data structures and algorithms with a focus on circuit and system design.

Rolf Drechsler was a member of Program Committees of numerous conferences including e.g., DAC, ICCAD, DATE, ASP-DAC, FDL, MEMOCODE, FMCAD, Symposiums Chair ISMVL 1999 and 2014, the Topic Chair for “Formal Verification” DATE 2004, DATE 2005, DAC 2010, as well as DAC 2011, and the Program Chair of FDL 2014. He is a co-founder of the Graduate School of Embedded Systems and he is the coordinator of the Graduate School “System Design” funded within the German Excellence Initiative. He received best paper awards at the Haifa Verification Conference (HVC) in 2006, the Forum on specification & Design Languages (FDL) in 2007 and 2010, the IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS) in 2010 and the IEEE/ACM International Conference on Computer-Aided Design (ICCAD) in 2013. He is a Fellow of the IEEE.