Senior Staff Software Engineer
Xilinx
San Jose, CA, USA

Automatic time sharing for area reduction in FPGA Synthesis

Friday, 11 December 2015 at 14:20 in BC 420

 

Abstract:

Field Programmable Gate Arrays (FPGAs) have dramatically increased their capacities in recent years to keep-up with the increasing complexity of designs. Despite that, they are constantly pushed toward their limits in terms of resource utilization to satisfy users’ increasing demand. In this context, the FPGA software tools need to carefully control their resource usage during synthesis.  In this work, we present a software methodology that takes advantage of inherent replication in designs to reduce their area footprint.

The proposed methodology automatically identifies the duplicated portions of the design and generates the equivalent functionality using a time multiplexing mechanism among multiple units. We have implemented a preliminary version of this optimization in Vivado and our initial results show CLB count reduction up to 50% for some designs and 17% lower resource utilization on average on a suite of representative designs.

The use of time multiplexing poses new challenges to maintain the QoR since the operating frequency of some large portions of the design needs to be multiplied several times. To address these challenges, we use sophisticated timing optimization techniques such as retiming, and take advantage of architecture optimizations such as time borrowing, which has been introduced in the Xilinx UltraScale+ devices.

We will present an early estimate of the QoR impact and also discuss the best place to apply such optimizations within Vivado synthesis or earlier in the tool flow as part of emerging SD tool flow with higher abstraction design entry.

About the speaker:

Henri Fraisse received a Ph.D. degree from the “Ecole Nationale des Telecomunications” in 1996.
He subsequently worked for the company BULL as a research software engineer where his main focus was to apply formal methods on hardware and software verification. In 1999, he joined a start-up company, “TRUSTED LOGIC”, focused on applying formal methods for smart card security.

In 2001, he joined Syncplicity where he worked on formal verification and FPGA synthesis with a focus on generic logic optimizations. In 2008, he joined Synopsys, where he worked first on FPGA synthesis and then on ASIC synthesis for Design Compiler. In 2012, he joined Xilinx (CTO research labs) where he is currently working on improving FPGA architectures and software tools.

His current domains of interest are FPGA architectures, logic optimizations, technology mapping and formal methods.