Position statement:

The Challenge of Exponential Complexity

Over the last fifty years we have been heading down Moore’s Law road, only scratching the surface of the possibilities offered by one technology node as we were already rushing to the next one (memories aside, at 180 nanometers, 2 years after introduction utilization of theoretical integration capacity was above 80%, at 22/20 nanometers, 2 years after introduction utilization is in the 20-30% range). Before the end of this decade, the theoretical integration capacity will be in the order of magnitude of the trillions of transistors on a single die and, before the end of the next decade, we will be at the “1” nanometer technology node (source: ITRS, 2014). This clearly makes sheer complexity the number one challenge to deal with in design, and design automation.

Raw performance of design tools must be continuously and thoroughly reviewed – contrary to some claims, nothing can be infinitely parallelized, and Amdahl’s law still stands, “alive and well” –, as well as their accuracy. New algorithms must be devised, and deployed for the critical phases of design implementation and closure; the quality of results does matter, as well as the time to results: the difference between the results achieved by current heuristics and optimal solutions keeps getting larger and must be “cured”.

At the same time design, and design automation are confronted with a second level of complexity: today designs are both analog AND digital, high performance AND low power, etc., thus posing simultaneously challenges that until very recently could be addressed separately. Design infrastructure, algorithms, methodologies, and flows must be increasingly versatile, and yet forward looking. Design exploration, before design implementation, is critical to understand the design landscape, “clean-up” the design – e.g. data flow, timing constraints, power intent – and quickly get to the best “starting point”.

Last, but not least, for the first time in the history of our industry, the breadth of active technology nodes is expanding; the pace at which emerging technology nodes get adopted is not only slowing down, it’s getting asymmetric, as more than 80% of design starts are at established nodes – 45/40 nanometers and above. As an example, the most advanced smartphones integrate ICs manufactured at process technology nodes ranging from 22/20 nanometers up to 1 micron, or that order of magnitude; more than 10 process technology nodes contribute critical ICs to one single electronic product. The technology node is no longer representative of the design, and design automation challenges: we can find designs with more than 10 voltage, supply, shutdown domains at both 22/20 and 180 nanometers. Design, and design automation must deal with this third level of complexity, as our industry cannot afford to develop and maintain multiple design implementation and verification platforms.

About the panel member:

Marco Casale-Rossi is a senior staff product marketing manager in Synopsys Design Group. Dr. Casale-Rossi joined Synopsys in 2005 after 20 years at STMicroelectronics Central R&D and ASIC R&D departments, where he participated in the development and deployment of some of the first “industrial” IC implementation EDA solutions. His last responsibility at ST was the management of the technology collaborations with the EDA partners. In the last few years, Dr. Casale-Rossi has contributed building Synopsys vision of the design and technology roadmap.