Intel Fellow and Director of Circuit Technology Research
Intel Labs
Hillsboro, Oregon, USA

Energy Efficient Designs with Wide Dynamic Range

Aggressive voltage scaling is a must for making major leaps in energy efficiency and power-constrained performance of microprocessors special-purpose engines. We need to span a very wide range of performance and power across a large number of diverse computing engines  and workloads with the fewest distinct designs. This requires our designs to achieve near-threshold-voltage (NTV) operation while supporting a wide voltage-frequency operating range with minimal impact on die cost. Breaking the 0.5V voltage barrier for designs in high-volume manufacturing (HVM) at scaled process technology nodes has been a major challenge.  We will discuss circuit and design technologies that can be combined with improvements in process and manufacturing technologies, to overcome the challenges posed by device parameter variations, supply noises, temperature excursions, aging-induced degradations, workload and activity changes, and reliability considerations. The four major pillars of energy-efficient designs with wide dynamic range are: (1) circuit/design optimizations for fine-grain multi-voltage & wide dynamic range, (2) fine-grain on-die power delivery & management, (3) dynamic adaptation & reconfiguration, and (4) dynamic on-die error detection & correction. Circuit/design optimizations must carefully balance voltage scalability with die area and maximum performance using intelligent metrics and methodologies. Furthermore, in many-core throughput engines, fine-grain multi-voltage/frequency capabilities can alleviate impacts of within-die variations on overall performance and energy-efficiency. Fine-grain on-die power delivery & management techniques enable efficient, distributed multi-voltage domains depending on circuit types and activity profiles. Then the threshold and supply voltages can be scaled more aggressively with minimal impact on leakage power. Also, the average operating voltage of the design can be reduced more dramatically since a few outlier circuits or transistors will no longer limit the voltage scaling of the majority of the design. Dynamic voltage-frequency adaptation helps reduce guardbands over the entire operating range resulting from worst-case assumptions about supply noises, temperature variations and aging. When combined with reconfigurations to bypass early-life or transient failures in circuits, and with error detection, profiling and correction, dynamic adaptation and resiliency can help push voltage/frequency limits much more aggressively than is possible using traditional means.  Silicon learnings for some of these technologies from proof-of-concept testchips and research prototypes will be presented.

 



About the speaker:

Dr. Vivek De is an Intel Fellow in Intel Labs, and Director of Circuit Technology Research. Currently he serves as the Director of the Circuits Research Lab in Hillsboro, Oregon, USA where he is responsible for providing strategic technical directions for long term research in future circuit technologies. He has 199 publications in refereed international conferences and journals, and 176 patents, with 28 more patents filed (pending). He is a Fellow of the IEEE.