Assistant Professor
Embedded Systems Laboratory, Director
Swiss Federal Institute of Technology, Lausanne, Switzerland
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Thermal-Aware Design for 3D Multi-Processor ICs in Datacenters

Continuous technical advances in manufacturing technologies are fueling the trend towards more powerful 3D Multi-Processor System-on-Chip (MPSoC) design for high-performance computing systems. However, 3D stacking originates larger heat densities beyond the standard 2D MPSoCs due to the higher power density resulting from the placement of computational units and storage components on top of each other, which can lead to degraded performance and even malfunctioning if thermal-aware design and thermal management are not properly handled at the different levels of system integration. During this talk I will describe the latest joint work conducted between EPFL, IBM Zürich and BU on the development of novel active liquid cooling management approaches for 3D MPSoC architectures, as a promising technology to overcome the limitations of traditional heat sinks for thermal control in forthcoming 3D chip stacks for high-performance computing systems and data-center designs. In the first part of the presentation, I will briefly present a compact transient thermal modeling approach for 3D MPSoC including inter-tier microchannels. Then, I will present a global hardware/software temperature controller for energy-efficient 3D MPSoC cooling. This controller includes a thermal-aware job scheduler, which balances the temperature across the system to maximize cooling efficiency. Furthermore, the proposed controller forecasts maximum system temperature, and uses this forecast to proactively set the liquid flow rate. Hence, the proposed controller avoids over- or under-cooling due to delays in reacting to temperature changes. The experiments on modeled 2- and 4-layered 3D MPSoCs show that the proposed global cooling controller prevents the system to exceed the given threshold temperature while reducing cooling energy by up to 50% and system-level energy by up to 21% in comparison to using a static worst-case flow rate setting. Moreover, our results show that temperature-aware load balancing reduces hot spots and gradients significantly better than load balancing or reactive thread migration in forthcoming 3D MPSoCs.

 

About the speaker:

David Atienza received his MSc and PhD degrees in Computer Science and Engineering from Complutense University of Madrid (UCM), Spain, and Inter-University Micro-Electronics Center (IMEC), Belgium, in 2001 and 2005, respectively. Currently, he is Professor and Director of the Embedded Systems Laboratory (ESL) at EPFL, Switzerland, and Adjunct Professor at the Computer Architecture and Systems Engineering Department of UCM. His research interests focus on design methodologies for low-power embedded systems and high performance Systems-on-Chip (SoC), including thermal-aware design for 2D and 3D Multi-Processor SoCs, system-level design methods and architectures for wireless body sensor networks, memory management and Network-on-Chip (NoC) interconnects. In these fields, he is co-author of more than 130 publications in prestigious journals and international conferences. He has received a Best Paper Award at the IEEE/IFIP VLSI-SoC 2009 Conference, and two Best Paper Award Nominations at the ICCAD 2006 and DAC 2005 conferences. He is an Associate Editor of IEEE Transactions on CAD, IEEE Letters on Embedded Systems and Elsevier Integration: The VLSI Journal. He is also an elected member of the Executive Committee of the IEEE Council of Electronic Design Automation (CEDA) since 2008 and a GOLD member of the Board of Governors of IEEE Circuits and Systems Society (CASS) since 2010.