Conference Proceedings

2024

1. C. Meng, M. Yu, W. Burleson, H. Wang and G. De Micheli, RareLS: Rarity-Reducing Logic Synthesis for Mitigating Hardware Trojan Threats, Proceedings ICCAD, Newark, NJ, 2024
2. A. Tempia Calvino and G. De Micheli, Algebraic and Boolean Methods for SFQ Superconducting Circuits, Proceedings ASPDAC, Incheon, Korea, 2024.
3. A. Tempia Calvino, G. Radi and Gi. De Micheli, In Medio Stat Virtus: Combining Boolean and Pattern Matching, Proceedings ASPDAC, Incheon, Korea, 2024.
4. R. Bairamkulov, A. Tempia Calvino and G. De Micheli, Towards Multiphase Clocking in Single-Flux Quantum Systems, Proceedings ASPDAC, Incheon, Korea, 2024.
5. C. Meng, H.Wang, Y. Mai, W. Qian, and G.De Micheli, VACSEM: Verifying Average Errors in Approximate Circuits Using Simulation-Enhanced Model Counting, DATE, Valencia 2024.
6. A. Tempia Calvino G.De Micheli, Scalable Logic Rewriting Using Dont Cares, DATE, Valencia 2024.
7. H. Wang, J. Cong and G. De Micheli, Quantum State Preparation Using an Exact CNOT Synthesis Formulation, DATE, Valencia 2024.
8. D. Marakkalage, E. Testa, W. Lau Neto, A. Mishchenko, G. De Micheli and L. Amaru, Scalable Sequential Optimization Under Observability Dont Cares, DATE, Valencia 2024.
9. R. Bairamkulov, M. Yu and G. De Micheli, Unleashing the Power of T1-cells in SFQ Arithmetic Circuits, DATE, Valencia 2024.
10. R. Bairamkulov, S.-Y. Lee, A. Tempia-Calvino, D. Marakkalage, M. Yu and G. De Micheli, Technology-Aware Logic Synthesis for Superconducting Electronics, DATE, Valencia 2024.
11. A. Costamagna, A. Mishchenko, S. Chatterjee and G. De Micheli, An Enhanced Resubstitution Algorithm for Area-Oriented Logic Optimization, ISCAS Singapore 2024.
12. R. Bairamkulov, M. Yu and G. De Micheli, Unleashing the Power of T1-cells in SFQ Arithmetic Circuits, DAC, San Francisco.
13. S.Y. Lee, A. Tempia Calvino, H. Riener and G. De Micheli, Late Breaking Results: Majority-Inverter Graph Minimization by Design Space Exploration, DAC San Francisco.
14. T. Koike-Akino, C. Meng, V. Cevher and G. De Micheli, Hardware-Efficient Quantization for Green Custom Foundation Models,ES-FoMo-II, International Conference on Machine Learning (ICML), Vienna, 2024
15. D. Marakkalage, M.Weber, S.-Y. Lee, R. Wille and G. De Micheli, Technology Mapping for Beyond-CMOS Circuitry with Unconventional Cost Functions, IEEE Nano, Girona 2024.
16. M. Yu, S.Carpov, A. Tempia-Calvino and G. De Micheli, On the synthesis of high-performance homomorphic Boolean Circuits,, Proceedings of WAHC: Workshop on Encrypted Computing & Applied Homomorphic Cryptography, Salt Lake city, 2024

2023

1. A. Tempia Calvino and G. De Micheli, Depth-Optimal Buffer and Splitter Insertion and Optimization in AQFP Circuits, Proceedings of ASPDAC, January 2023.
2. D. Sudara Marakkalage and G. De Micheli, Fanout-Bounded Logic Synthesis for Emerging Technologies - A Top-Down Approach, Proceedings of DATE, March 2023.
3. M. Yu and G. De Micheli, Generating Lower-Cost Garbled Circuits: Logic Synthesis Can Help, HOST, 2023.
4. R. Bairamkulov and G. De Micheli, Compund Gates for Pipeline Depth Optimization in Single Flux Quantum Integrated Systems, Proceedings of GVLSI 2023
5. A.Tempia Calvino, Al. Mishchenko, H. Schmit, E. Mahintorabi, G. De Micheli1, and X. Xu, Improving Standard-Cell Design Flow using Factored Form Optimization, DAC 2023
6. G. De Micheli, Logic Synthesis for Emerging Technologies, Proceedings ASICON, Nanjing, 2023
7. G. De Micheli, Cyclical Progress in Design and Technology, Proceedings ICTA, Hefei, 2023
8. Alessandro Tempia Calvino and Giovanni De Micheli, Technology Mapping using Multi-output Library cells, Proceedings ICCAD, 2023.
9. Mingfei Yu and Giovanni De Micheli, Striving for both quality and Speed: Logic Synthesis for practical garbled circuits, Proceedings ICCAD, 2023
10. Rassul Bairamkulov, Alessandro Tempia Calvino and Giovanni De Micheli, Synthesis of SFQ Circuits with Compound Gates, Proceedings of VLSI-SOC, Dubai, 2023.

2022

1. H. Riener, S.-Y. Lee, A. Mishchenko and G.De Micheli Boolean Rewriting Strikes Back: Reconvergence- Driven Windowing meets Resynthesis, Proceedings ASPDAC, January 2022.
2. F. Mozafari, Y. Yang and G.De Micheli Efficient preparation of Cyclic Quantum States Proceedings ASPDAC, January 2022.
3. A. Tempia Calvino, H. Riener, S.Rai A. Kumar and G. De Micheli A Versatile Mapping Approach for Technology Mapping and Graph Optimization, Proceedings ASPDAC, January 2022
4. G. Meuli, V. Possani, R. Singh, S.-Y. Lee, A. Tempia Calvino, D. Marakkalage, P. Vuillod, L. Amaru, S. Chase, J. Kawa and G. De Micheli, Majority-based Design Flow for AQFP Superconducting Family, DATE 2022
5. B. Schmitt and G. De Micheli, tweedledum: A Compiler Companion for Quantum Computing, DATE 2022
6. A. Costamagna and G. De Micheli, Logic Synthesis From Incomplete Specifications Using Disjoint Support Decomposition, Prime, Cagliari, 2022
7. S.-Y. Lee, H. Riener and G. De Micheli, Beyond Local Optimality of Buffer and Splitter Insertion for AQFP Circuits, DAC 2022

2021

1. E. Testa, S-Y. Lee, H. Riener and G. De Micheli, Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits, ASPDAC, Tokyo, Japan, 2021.
2. S. Rai, H. Riener, G. De Micheli and A. Kumar, Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies, DATE 2021 Grenoble, France, February 2021.
3. B. Schmitt, A. Javadi-Abhari and G. De Micheli, Compilation flow for classically-defined quantum oper- ations, DATE 2021 Grenoble, France, February 2021.
4. B. Schmitt, F. Mozafari, G. Meuli, H. Riener and G. De Micheli, From Boolean functions to quantum circuits: A scalable quantum compilation flow in C++, DATE 2021 Grenoble, France, February 2021.
5. S-Y Lee, H. Riener and G. De Micheli, Logic Resynthesis of Majority-Based Circuits by Top-Down De- composition, DDECS, Vienna, April 2021.
6. D. Marakkalage, H. Riener and G. De Micheli, Optiomizing Adiabatic Quantum Flux Parametron (AQFP) Circuits using Exact Database, NanoArch, 2021.
7. L. Amaru, V. Possani, E. Testa, F. Marranghello, C.Casares, J. Luo, P. Vuillod, A. Mishchenko and G. De Micheli, LUT-Based Optimization For ASIC Design Flow, Design Automation Conference, San Francisco, CA, 2021.

2020

1. E. Testa, M. Soeken, H. Riener, L. Amaru, G. De Micheli, A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks, DATE 2020 Grenoble, France, March 2020.
2. E. Testa, S. Lubaba Noor, O. Zografos, M. Soeken, F. Catthoor, A. Naeemi, G. De Micheli, Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic, DATE 2020 Grenoble, France, March 2020.
3. L. Amaru, F. Marranghello, E. Testa, C. Casares, V. Possani, J. Luo, P. Vuillod, A. Mishchenko, G. De Micheli, SAT-Sweeping Enhanced for Logic Synthesis, DAC 2020 San Francisco, USA.
4. G. Meuli, M. Soeken, M. Roetteler, G. De Micheli, Enumerating Optimal Quantum Circuits using Spectral Classification ISCAS 2020 Seville, Spain, October 2020.
5. I. Ny Hanitra, D. Demarchi, S. Carrara, G. De Micheli, Emulator Design and Generation of Synthetic Dataset in Multi-Ion Sensing, ISCAS 2020 Seville, Spain, October 2020.
6. F. Mozafari, M. Soeken, H. Riener, G. De Micheli, Automatic Uniform Quantum State Preparation Using Decision Diagrams, ISMVL 2020 Miyazaki, Japan, November 2020.
7. B. Schmitt, M. Soeken, G. De Micheli, Symbolic Algorithms for Token Swapping, ISMVL 2020 Miyazaki, Japan, November 2020.

2019

1. Z. Chu, W. Haaswijk, M. Soeken, Y. Xia, L. Wang, and G. De Micheli, Exact Synthesis of Boolean Functions in Majority-of-Five Forms, in 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, May 2019.
2. H. Riener, W. Haaswijk, A. Mishchenko, G. De Micheli, and M. Soeken, On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis, DATE 2019 Firenze, Italy, March 2019.
3. G. Meuli, M. Soeken, M. Roetteler, N. Bjorner, G. De Micheli, Reversible Pebbling Game for Quantum Memory Management, DATE 2019, Firenze, Italy, March 2019.
4. E. Testa, L. Amaru, M. Soeken, A. Mishchenko, P. Vuillod, J. Luo, C. Casares, P.-E. Gaillardon, G. De Micheli, Scalable Boolean Methods in a Modern Synthesis Flow, DATE 2019, Firenze, Italy, March 2019.
5. H. Riener, E. Testa, W. Haaswijk, A. Mishchenko, L. Amarù, G. De Micheli, and M. Soeken, Scalable Generic Logic Synthesis: One Approach to Rule Them All, DAC 2019, Las Vegas, USA, June 2019.
6. E. Testa, M. Soeken, L. Amaru, G. De Micheli, Reducing the Multiplicative Complexity in Logic Networks for Cryptography and Security Applications, DAC 2019, Las Vegas, USA, June 2019.
7. G. Meuli, M. Soeken, M. Roetteler, G. De Micheli, Resource constrained oracle synthesis for quantum computers, Quantum Physics and Logic (QPL), Orange CA, USA, June 10–14, 2019.
8. K. Smith, M. Soeken, B. Schmitt, G. De Micheli, M. Thornton, Using ZDDs in the mapping of quantum circuits, Quantum Physics and Logic (QPL), Orange CA, USA, June 10–14, 2019.
9. F. Criscuolo, M.Galfione, S. Carrara; G. De Micheli : All-solid-state Reference Electrodes for analytical applications, 8th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI), Otranto, Italy, June 13-14, 2019
10. G. Meuli, B. Schmitt, R. Ehlers, H. Riener, G. De Micheli, Evaluating ESOP Optimization Methods in Quantum Compilation Flows, Reversible Computing (RC), Lausanne, Switzerland, June 24-25, 2019.
11. I. Ny Hanitra, F. Criscuolo, S. Carrara, G. De Micheli, Multi-Target Electrolyte Sensing Front-End for Wearable Physical Monitoring, 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME), Lausanne, Switzerland, July 2019
12. M. Imani, J. Morris, S. Bosch, H. Shu, G. De Micheli, T. Rosing, AdaptHD: Adaptive Efficient Training for Brain-Inspired Hyperdimensional Computing, Conference BioCAS, Nara, Japan, October 17-19, 2019
13. F. Criscuolo, F. Cantu, I. Taurino, S. Carrara, G. De Micheli, Flexible sweat sensors for non-invasive optimization of lithium dose in psychiatric disorders, Conference IEEE Sensors 2019, Montreal, Canada, October 27-30, 2019.
14. M. Soeken, E. Testa and M. Miller, A Hybrid Method for Spectral Translation Equivalent Boolean Functions, Pacific Rim Conference on Communication Computers and Signal Processing, 2019.
15. G. Meuli, M. Soeken, E. Campbell, M. Roettele and G. De Micheli, The Role of Multiplicative Complexity in Compiling Low T-count Oracle Circuits, ICCAD, 2019.

2018

1. L. Amaru, M. Soeken, P. Vuillod, J. Luo, A. Mishchenko, J. Olson, R. Brayton and G. De Micheli. Improvements to Boolean resynthesis, Design, Automation and Test in Europe, Dresden, Germany, pp. 755-790, 2018.
2. Z. Chu, M. Soeken, Y. Xia and G. De Micheli. Functional decomposition using majority, 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), Jeju Island, Korea, 2018.
3. G. Meuli, M. Soeken, M. Roetteler, N. Wiebe and G. De Micheli. A best-fit mapping algorithm to facilitate ESOP-decomposition in Clifford+T quantum network synthesis, 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 664-669, Jeju Island, Korea, 2018.
4. W. J. Haaswijk, L. Amarù, P. Vuillod, J. Luo, M. Soeken, G. De Micheli, Integrated ESOP Refactoring for Industrial Designs, Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS). Bordeaux, France. December 2018.
5. F. Criscuolo, I. Taurino, S. Carrara, G. De Micheli, A novel electrochemical sensor for non-invasive monitoring of lithium levels in mood disorders, Proceedings of the 40th International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC). pp. 3825-3828, Honolulu, HI, USA. July 2018.
6. W.J. Haaswijk, E. Collins, B. Seguin, M. Soeken, F. Kaplan, S. Susstrunk, G. De Micheli, Deep Learning for Logic Optimization Algorithms, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS). pp. 1-4., Florence, Italy. May 2018.
7. W. J. Haaswijk, A. Mishchenko, M. Soeken, G. De Micheli, SAT Based Exact Synthesis using DAG Topology Families, Proceedings of the ACM/IEEE Design Automation Conference (DAC), pp. 1-6. San Francisco, CA, USA. June 2018.
8. G. Meuli, M. Soeken, G. De Micheli, SAT-based CNOT, T Quantum Circuit Synthesis'', International Conference on Reversible Computation, Reversibile Computation, pp. 175-188, Leicester, UK. August 2018.
9. M.I. Ny Hanitra, L. Lobello, F. Stradolini, A. Tuoheti, F. Criscuolo, T. Kilic, D. Demarchi, S. Carrara, G. De Micheli, A Flexible Front-End for Wearable Electrochemical Sensing, IEEE International Symposium on Medical Measurements and Applications (MeMeA), pp. 1-6. Rome, Italy. June 2018.
10. G.V. Resta, Y. Balaji, D. Lin, I.P. Radu, F. Catthoor, P.-E. Gaillardon, G. De Micheli, Doping-free complementary inverter enabled by 2D WSe2 electrostatically-doped reconfigurable transistors , 76th Device Research Conference (DRC), p. 1-2. Santa Barbara, CA, USA. June 2018.
11. G. V. Resta, J. R. Gonzalez, Y. Balaji, T. Agarwal, D. Lin, F. Catthor, I.P. Radu, G. De Micheli, P.-E. Gaillardon, Towards high-performance polarity-controllable FETs with 2D materials, Design, Automation and Test in Europe Conference and Exhibition (DATE), pp. 637-641. Dresden, Germany. March 2018.
12. M. Soeken, W. J. Haaswijk, E. Testa, A. Mishchenko, L. Amaru, R. Brayton, G. De Micheli, Practical Exact Synthesis, Proceedings of the 2018 Design, Automation and Test In Europe Conference and Exhibition (DATE). pp. 309-314. 2018.
13. I. Tzouvadaki, A. Tuoheti, G. De Micheli, D. Demarchi, S. Carrara, Portable Memristive Biosensing System as Effective Point-of-Care Device for Cancer Diagnostics, Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, Florence, Italy. May 2018.
14. C. Yu, C.-C. Huang, G.-J. Nam, M. Choudhury, V.N. Kravets, A. Sullivan, M. Ciesielski, G. De Micheli, End-to-End Industrial Study of Retiming, IEEE Computer Society Annual Symposium on VLSI. pp. 203-208, Hong Kong, China. July 2018.
15. C. Yu, H. Riener, F. Stradolini, G. De Micheli, Generating Safety Guidance for Medical Injection with Three-Compartment Pharmacokinetics Model, Proceedings of the IEEE Computer Society Annual Symposium on VLSI, IEEE Computer Society Annual Symposium on VLSI. pp. 299-304, Hong Kong, China. July 2018.
16. C. Yu, H. Xiao, G. De Micheli, Developing Synthesis Flows without Human Knowledge, Proceedings of the ACM/IEEE Design Automation Conference, pp. 1-6, San Francisco, CA, USA. June 2018.
17. H. Riener, E. Testa, L. Amaru, M. Soeken, and G. De Micheli, Size Optimization of MIGs with an Application to QCA and STMG Technologies, 14th IEEE / ACM International Symposium on Nanoscale Architectures (NANOARCH), Athens, Greece, 2018.

2017

1. E. Testa, M. Soeken, O. Zografos, F. Catthoor and G. De Micheli. Exact Synthesis for Logic Synthesis Applications with Complex Constraints. 26th International Workshop on Logic & Synthesis (IWLS), Austin, Texsas, USA, 2017.
2. I. Tzouvadaki, N. Aliakbarinodehi, G. De Micheli and S. Carrara. Memristive Aptasensors for Theranostics. International Conference on Memristive Materials, Devices and Systems, Athens, Greece, 2017.
3. B. Donato, F. Stradolini, A. Tuoheti, F. Angiolini and D. Demarchi et al. Raspberry Pi Driven Flow-Injection System for Electrochemical Continuous Monitoring Platforms. IEEE Biomedical Circuits and Systems Conference (BioCAS), Turin, Italy, 2017.
4. F. Criscuolo, I. Taurino, T. Kili, S. Carrara and G. De Micheli. An electrochemical sensor for quantitative analysis of Rhesus D antibodies in blood. 7th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI), Vieste, Italy, 2017.
5. A. Ibrahim, D. Doy, C. Loureiro, E. Pignat and F. Angiolini et al. Inexpensive 1024-Channel 3D Telesonography System on FPGA. IEEE Biomedical Circuits and Systems Conference (BioCAS), Turin, Italy, 2017.
6. A. Ibrahim, W. Simon, D. Doy, E. Pignat and F. Angiolini et al. Single-FPGA complete 3D and 2D medical ultrasound imager. 2017 Conference on Design and Architectures for Signal and Image processing (DASIP), Dresden, Germany, 2017.
7. G. Meuli, M. Soeken, P.-E. Gaillardon and G. De Micheli. A Compiler for Parallel and Resource-Constrained Programmable in-Memory Computing. 26th International Workshop on Logic & Synthesis (IWLS), Austin, Texsas, USA, 2017.
8. S. Naus, I. Tzouvadaki, P.-E. Gaillardon, A. Biscontini and G. De Micheli et al. An Efficient Electronic Measurement Interface for Memristive Biosensors. IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, Maryland, USA, 2017.
9. L. Amar, M. Soeken, P. Vuillod, J. Luo and A. Mishchenko et al. Enabling exact delay synthesis. 36th IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Irvine, California, USA, 2017.
10. E. Testa, O. Zografos, M. Soeken, A. Vaysset and M. Manfrini et al. Inverter Propagation and Fan-Out Constraints for Beyond-CMOS Majority-Based Technologies. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Bochum, Germany, 2017.
11. M. Soeken, M. Roetteler, N. Wiebe and G. De Micheli. Hierarchical Reversible Logic Synthesis Using LUTs. 54th ACM/IEEE Design Automation Conference (DAC), Austin, Texsas, USA, 2017.
12. M. Soeken, P.-E. Gaillardon and G. De Micheli. RM₃ based logic synthesis. IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, Maryland, USA, 2017.
13. Z. Chu, X. Tang, M. Soeken, A. Petkovska and G. Zgheib et al. Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains. Great Lakes Symposium on VLSI (GLVLSI), Banff, Alberta, Canada, 2017.
14. W. Haaswijk, E. Testa, M. Soeken and G. De Micheli. Classifying Functions with Exact Synthesis. IEEE 47th International Symposium on Multiple-Valued Logic (ISMVL), Novi Sad, Serbia, 2017.
15. F. Angiolini, A. Ibrahim, W. Simon, A. C. Yuzuguler and M. Arditi et al. 1024-Channel 3D Ultrasound Digital Beamformer in a Single 5W FPGA. 2017 Design, Automation & Test in Europe Conference & Exhibition (DATE), EPFL, Lausanne, Switzerland, 2017.
16. F. Criscuolo, I. Taurino, T. Kilic, S. Carrara and G. De Micheli. An electrochemical sensor for quantitative analysis of Rhesus D antibodies in blood. 7th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI), Vieste, Italy, 2017.
17. X. Tang, G. De Micheli and P.-E. Gaillardon. Optimization Opportunities in RRAM-based FPGA Architectures. IEEE 8th Latin American Symposium on Circuits & Systems (LASCAS), Bariloche, Argentina, 2017.
18. O. Zografos, A. De Meester, E. Testa, M. Soeken and P.-E. Gaillardon et al. Wave Pipelining for Majority-based Beyond-CMOS Technologies. Design, Automation & Test in Europe (DATE), Lausanne, Switzerland, 2017.
19. M. Soeken, M. Roetteler, N. Wiebe and G. De Micheli. Design Automation and Design Space Exploration for Quantum Computers. Design, Automation & Test in Europe (DATE), Lausanne, Switzerland, Design Automation and Test in Europe Conference and Exhibition, 2017.
20. M. Soeken, G. De Micheli and A. Mishchenko. Busy Man's Synthesis: Combinational Delay Optimization With SAT. Design, Automation & Test in Europe (DATE), Lausanne, Switzerland, Design Automation and Test in Europe Conference and Exhibition, 2017.
21. S. Shirinzadeh, M. Soeken, P.-E. Gaillardon, G. De Micheli and R. Drechsler. Endurance Management for Resistive Logic-In-Memory Computing Architectures. Design, Automation & Test in Europe (DATE), Lausanne, Switzerland, Design Automation and Test in Europe Conference and Exhibition, 2017.
22. X. Tang, E. Giacomin, G. De Micheli and P.-E. Gaillardon. Physical Design Considerations of One-level RRAM-based Routing Multiplexers. International Symposium on Physical Design (ISPD), Portland, Oregon, USA, 2017.
23. L. Amaru, M. Soeken, W. Haaswijk, E. Testa and P. Vuillod et al. Multi-level Logic Benchmarks: An Exactness Study. 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), Chiba, Japan, Asia and South Pacific Design Automation Conference Proceedings, 2017.
24. W. Haaswijk, M. Soeken, L. Amaru, P.-E. Gaillardon and G. De Micheli. A Novel Basis for Logic Rewriting. 22nd Asia and South Pacific Design Automation Conference (ASP-DAC), Chiba, Japan, Asia and South Pacific Design Automation Conference Proceedings, 2017.

2016

1. A. C. Yuzuguler, W. Simon, A. Ibrahim, F. Angiolini and M. Arditi et al. Demo: Efficient Delay and Apodization for on-FPGA 3D Ultrasound. Conference on Design and Architectures for Signal and Image Processing (DASIP), Rennes, France, 2016.
2. A. C. Yuzuguler, W. Simon, A. Ibrahim, F. Angiolini and M. Arditi et al. Single-FPGA 3D Ultrasound Beamformer. 26th International Conference on Field-Programmable Logic and Applications (FPL), Lausanne, Switzerland, 2016.
3. W. Simon, A. C. Yuzuguler, A. Ibrahim, F. Angiolini and M. Arditi et al. Single-FPGA, Scalable, Low-Power, and High-Quality 3D Ultrasound Beamformer. 26th International Conference on Field-Programmable Logic and Applications (FPL), Lausanne, Switzerland, 2016.
4. A. Ibrahim, F. Angiolini, M. Arditi, J.-P. Thiran and G. De Micheli. Apodization Scheme for Hardware-Efficient Beamformer. 12th Conference on PhD Research in Microelectronics and Electronics (PRIME), Lisbon, Portugal, 2016.
5. I. Tzouvadaki, X. Lu, G. De Micheli, S. Ingebrandt and S. Carrara. Nano-fabricated memristive biosensors for biomedical applications with liquid and dried samples. IEEE 38th Annual International Conference of the Engineering in Medicine and Biology Society (EMBC), Orlando, Florida, USA, 2016.
6. E. Testa, M. Soeken, L. Amaru, P.-E. Gaillardon and G. De Micheli. Inversion Minimization in Majority-Inverter Graphs. 25th International Workshop on Logic & Synthesis (IWLS), Austin, Texas, USA, 2016.
7. W. J. Haaswijk, M. Soeken, L. Amaru, P.-E. Gaillardon and G. De Micheli. LUT Mapping and Optimization for Majority-Inverter Graphs. 25th International Workshop on Logic & Synthesis (IWLS), Austin, Texas, USA, 2016.
8. M. Soeken, P. Raiola, B. Sterin, B. Becker and G. De Micheli et al. SAT-Based Combinational and Sequential Dependency Computation. 12th Haifa Verification Conference (HVC 2016), Haifa, Israel, 2016.
9. F. Stradolini, E. Lavalle, G. De Micheli, P. Motto Ros and D. Demarchi et al. Paradigm-Shifting Players for IoT: Smart-Watches for Intensive Care Monitoring. 6th International Conference on Wireless Mobile Communication and Healthcare (MobiHealth), Milan, Italy, 2016.
10. A. Petkovska, M. Soeken, G. De Micheli, P. Ienne and A. Mishchenko. Fast Hierarchical NPN Classification. International Conference on Field-Programmable Logic and Applications, Lausanne, Switzerland, 2016.
11. M. Casale-Rossi, G. De Micheli, A. Domic, E. Macii and D. Rossi et al. Panel: Looking Backwards and Forwards. Design, Automation and Test in Europe Conference and Exhibition (DATE), Dresden, Germany, Design, Automation, and Test in Europe Conference and Exhibition, 2016.
12. A. Petkovska, A. Mishchenko, M. Soeken, G. De Micheli and R. K. Brayton et al. Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications. International Conference on Computer Aided Design (ICCAD), Austin, Texas, USA, 2016.
13. E. Testa, M. Soeken, O. Zografos, L. Amaru and P. Raghavan et al. Inversion optimization in majority-inverter graphs. IEEE/ACM International Symposium on Nanoscale Archituectures (NANOARCH), Beijing, China, 2016.
14. M. Soeken, N. Abdessaied and G. De Micheli. Enumeration of reversible functions and its application to circuit complexity. 8th Conference on Reversible Computation (RC), Bologna, Italy, 2016.
15. M. Soeken, A. Mishchenko, A. Petkovska, B. Sterin and P. Ienne et al. Heuristic NPN classification for large functions using AIGs and LEXSAT. 19th International Conference on Theory and Applications of Satisfiability Testing (SAT), Bordeaux, France, 2016.
16. I. Tzouvadaki, A. Vallero, F. Puppo, G. De Micheli and S. Carrara. Resistance impact by long connections on electrical behavior of integrated Memristive Biosensors. IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, 2016.
17. S. Ghoreishizadeh, P. Georgiu, S. Carrara and G. De Micheli. An Integrated Platform for Differential Electrochemical and ISFET Sensing. IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, 2016.
18. F. Stradolini, T. Elboshra, A. Biscontini, G. De Micheli and S. Carrara. Simultaneous Monitoring of Anesthetics and Therapeutic Compounds with a Portable Multichannel Potentiostat. IEEE International Symposium on Circuits and Systems (ISCAS), Montreal, Canada, 2016.
19. K. Kang, S. Park, J.-B. Lee, L. Benini and G. De Micheli. A Power-Efficient 3-D On-Chip Interconnect for Multi-Core Accelerators with Stacked L2 Cache. Design, Automation and Test in Europe (DATE), Dresden, Germany, Design, Automation, and Test in Europe Conference and Exhibition, 2016.
20. A. Chattopadhyay, L. Amarù, M. Soeken, P.-E. Gaillardon and G. De Micheli. Notes on Majority Boolean Algebra. IEEE International Symposium on Multi-Valued Logic (ISMVL), Sapporo, Japan, 2016.
21. M. Soeken, S. Shirinzadeh, P.-E. Gaillardon, L. Amarù and R. Drechsler et al. An MIG-based Compiler for Programmable Logic-in-Memory Architectures. 53rd Design Automation Conference (DAC), Austin, Texas, USA, 2016.
22. L. Amarù, P.-E. Gaillardon and G. De Micheli. Majority-based Synthesis for Nanotechnologies. 21st Asia and South Pacific Design Automation Conference (ASP-DAC 2016), Macao SAR, China, Asia and South Pacific Design Automation Conference Proceedings, 2016.
23. P.-E. Gaillardon, L. Amarù, A. Siemon, E. Linn and R. Waser et al. The Programmable Logic-in-Memory (PLiM) Computer (Invited). Design, Automation & Test in Europe Conference (DATE), Dresden, Germany, Design, Automation, and Test in Europe Conference and Exhibition, 2016.
24. M. Soeken, L. Amarù, P.-E. Gaillardon and G. De Micheli. Optimizing Majority-Inverter Graphs with Functional Hashing. Design, Automation & Test in Europe Conference (DATE), Dresden, Germany, Design, Automation, and Test in Europe Conference and Exhibition, 2016.
25. L. Amaru, P.-E. Gaillardon, R. Wille and G. De Micheli. Exploiting Inherent Characteristic of Reversible Circuits for Faster Combinational Equivalence Checking. Design, Automation & Test in Europe Conference (DATE), Dresden, Germany, Design, Automation, and Test in Europe Conference and Exhibition, 2016.

2015

1. G. De Micheli. NANO-TERA.CH: Electronic Technology for Health Management. 9th Jordanian International Electrical and Electronics Engineering Conference (JIEEEC 2015), Amman, Jordan, 2015.
2. I. P. Radu, O. Zografos, A. Vaysset, F. Ciubotaru and J. Yan et al. Spintronic Majority Gates. IEEE International Electron Devices Meeting (IEDM), 2015.
3. I. Tzouvadaki, F. Puppo, M.-A. Doucey, G. De Micheli and S. Carrara. Modeling Memristive Biosensors. IEEE Sensors 2015, Busan, South Korea, 2015.
4. F. Basilotta, S. Riario, F. Stradolini, I. Taurino and D. Demarchi et al. Wireless Monitoring in Intensive Care Units by a 3D-Printed System with Embedded Electronics. IEEE/CAS-EMB Biomedical Circuits and Systems Conference (BioCAS 2015), Atlanta, Georgia, USA, 2015.
5. C. Baj-Rossi, A. Cavallini, T. Rezzonico Jost, M. Proietti and F. Grassi et al. Biocompatible Packagings for Fully Implantable Multi-Panel Devices for Remote Monitoring of Metabolism. Biomedical Circuits and Systems Conference (BiOCAS 2015), Atlanta, Georgia, USA, 2015.
6. G. Sanzo, I. Taurino, G. Favero, F. Mazzei and G. De Micheli et al. Highly Sensitive Electrodic Materials Based on Pt Nanoflowers Grown on Pt Nanospheres for Biosensor Development. 15th International IEEE Conference on Nanotechnology (NANO 2015), Rome, Italy, 2015.
7. B. Staar, M. Schirmer, C. Baj-Rossi, G. De Micheli and S. Carrara et al. A neural approach to drugs monitoring for personalized medicine. International Joint Conference on Neural Networks 2015 (IJCNN), Killarney, Ireland, 2015.
8. I. Tzouvadaki, N. Madaboosi, R. R. G. Soares, J. P. Conde and G. De Micheli et al. Bio-functionalization study of Memristive- Biosensors for Early Detection of Prostate Cancer. IEEE 11th Conference on PhD Research in Microelectronics and Electronics (PRIME 2015), Glasgow, Scotland, UK, 2015.
9. N. Aliakbari, G. De Micheli and S. Carrara. Optimized Electrochemical Detection of Anti-Cancer Drug by Carbon Nanotubes or Gold Nanoparticles. IEEE PRIME 2015, Glasgow, Scotland, UK, 2015.
10. X. Tang, P.-E. Gaillardon and G. De Micheli. Accurate Power Analysis for Near-Vt RRAM-based FPGA. 25th International Conference on Field-programmable Logic and Applications (FPL), London, UK, 2015.
11. P.-E. Gaillardon, J. Zhang, M. De Marchi and G. De Micheli. Towards Functionality-Enhanced Devices: Controlling the Modes of Operation in Three-Independent-Gate Transistors (invited). 10th IEEE Nanotechnology Materials and Devices Conference (NMDC), Anchorage, Alaska, USA, 2015.
12. J. Zhang, P.-E. Gaillardon and G. De Micheli. A Surface Potential and Current Model for Polarity-Controllable Silicon Nanowire FETs. 45th European Solid-State Device Conference (ESSDERC), Graz, Austria, 2015.
13. X. Tang, P.-E. Gaillardon and G. De Micheli. FPGA-SPICE: A Simulation-based Power Estimation Framework for FPGAs. 33rd IEEE International Conference on Computer Design (ICCD), New York, New York, USA, 2015.
14. O. Zografos, B. Sorée, A. Vaysset, S. Cosemans and L. Amarù et al. Design and Benchmarking of Hybrid CMOS-Spin Wave Device Circuits Compared to 10nm CMOS. 15th International IEEE Conference on Nanotechnology (NANO), Rome, Italy, 2015.
15. H. Ghasemzadeh, P.-E. Gaillardon, J. Zhang, G. De Micheli and E. Sanchez et al. On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Montpellier, France, 2015.
16. A. Lotfi, D. Demarchi, F. Puppo, G. De Micheli and S. Carrara et al. Reliable Redundancy with Memristive-Biosensors to achieve Statistical Significance in Immunosensing. 6th IEEE International Workshop on Advances in Sensors and Interfaces (IWASI), Gallipoli, Italy, 2015.
17. G. De Micheli. E-Health: From Sensors to Systems. Transducers 2015, Anchorage, Alaska, 2015.
18. A. Ibrahim, A. Simalatsar, S. Skalistis, F. Angiolini and M. Arditi et al. Assessment of Image Quality vs. Computation Cost for Different Parameterizations of Ultrasound Imaging Pipelines. 6th Workshop on Medical Cyber-Physical Systems, Seattle, WA, USA, 2015.
19. W. Haaswijk, L. Amarù, P.-E. Gaillardon and G. De Micheli. NEM Relay Design with Biconditional Binary Decision Diagrams. IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH '15), Boston, Massachusetts, USA, 2015.
20. L. Amaru, P.-E. Gaillardon, A. Mishchenko, M. Ciesielski and G. De Micheli. Exploiting Circuit Duality to Speed Up SAT. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Montpellier, France, 2015.
21. L. Amarù, P.-E. Gaillardon and G. De Micheli. The EPFL Combinational Benchmark Suite. 24th International Workshop on Logic & Synthesis (IWLS), Mountain View, California, USA, 2015.
22. S. Miryala, V. Tenace, A. Calimera, E. Macii and M. Poncino et al. Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization. 25th Great Lakes Symposium on VLSI (GLSVLSI), Pittsburgh, Pennsylvania, USA, 2015.
23. S. Rahimian Omam, X. Tang, P.-E. Gaillardon and G. De Micheli. A Study on Buffer Distribution for RRAM-based FPGA Routing Structures. 6th IEEE Latin American Symposium on Circuits and Systems (LASCAS 2015), Montevideo, Uruguay, 2015.
24. G. De Micheli, J. Bagherli, T. Collette, A. Domic and H. Symanzik et al. Panel: The Future of Electronics, Semiconductors, and Design in Europe. Design, Automation & Test in Europe (DATE 2015), Grenoble, France, 2015.
25. L. Amarù, P.-E. Gaillardon and G. De Micheli. Boolean Logic Optimization in Majority-Inverter Graphs. Design Automation Conference (DAC), San Francisco, California, USA, 2015.
26. A. Chattopadhyay, A. Littarru, L. Amarù, P.-E. Gaillardon and G. De Micheli. Reversible Logic Synthesis via Biconditional Binary Decision Diagrams. IEEE International Symposium on Multiple-Valued Logic (ISMVL), Waterloo, Ontario, Canada, 2015.
27. S. Carrara, C. Baj-Rossi, S. S. Ghoreishizadeh, S. Riario and G. Surrel et al. Full System for Translational Studies of Personalized Medicine with Free-Moving Mice (invited). International Symposium on Circuits and Systems (ISCAS), Lisbon, Portugal, 2015.
28. H. Ghasemzadeh, P.-E. Gaillardon and G. De Micheli. Fault Modeling in Controllable Polarity Silicon Nanowire Circuits. Design, Automation & Test in Europe (DATE 2015), Grenoble, France, 2015.
29. P.-E. J. M. Gaillardon, X. Tang, J. Sandrini, M. Thammasack and S. Rahimian Omam et al. A Ultra-Low-Power FPGA Based on Monolithically Integrated RRAMs (invited). Design, Automation & Test in Europe (DATE 2015), Grenoble, France, 2015.
30. A. Ibrahim, P. Hager, F. Angiolini, M. Arditi and L. Benini et al. Tackling the Bottleneck of Delay Tables in 3D Ultrasound Imaging. Design, Automation & Test in Europe (DATE 2015), Grenoble, France, 2015.
31. L. Amaru, A. Petkovska, P.-E. Gaillardon, D. Novo and P. Ienne et al. Majority-Inverter Graph for FPGA Synthesis. 19th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI 2015), Yilan, Taiwan, 2015.
32. J. Broc, P.-E. Gaillardon, L. Amarù, J. J. Murillo and K. Palem et al. A Fast Pruning Technique for Low-Power Inexact Circuit Design. 6th IEEE Latin American Symposium on Circuits and Systems (LASCAS 2015), Montevideo, Uruguay, 2015.
33. L. Amarù, G. Hills, P.-E. Gaillardon, S. Mitra and G. De Micheli. Multiple Independent Gate FETs: How Many Gates Do We Need?. 20th Asia and South Pacific Design Automation Conference (ASP-DAC 2015), Chiba/Tokyo, Japan, 2015.

2014

1. I. Taurino, A. Magrez, L. Forró, G. De Micheli and S. Carrara. Direct and selective synthesis of a wide range of carbon nanomaterials by CVD at CMOS compatible temperatures. 14th IEEE International Conference on Nanotechnology, Toronto, Ontario, Canada, 2014.
2. H. Ghasemzadeh, P.-E. Gaillardon, M. Yazdani and G. De Micheli. Fast Process Variation Analysis in Nano-Scaled Technologies Using Column-Wise Sparse Parameter Selection. IEEE/ACM International Symposium on Nanoscale Architectures (NanoArch), Paris, France, 2014.
3. X. Tang, J. Zhang, P.-E. Gaillardon and G. De Micheli. TSPC Flip-Flop Circuit Design with Three-Independent-Gate Silicon Nanowire FETs. IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, Austrailia, 2014.
4. O. Zografos, P.-E. Gaillardon and G. De Micheli. Novel Grid-Based Power Routing Scheme for Regular Controllable-Polarity FET Arrangements. IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, Austrailia, 2014.
5. P.-E. Gaillardon, X. Tang and G. De Micheli. Novel Configurable Logic Block Architecture Exploiting Controllable-Polarity Transistors, (invited). 9th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC'14), Montpellier, France, 2014.
6. P.-E. Gaillardon, L. Amarù and G. De Micheli. A New Basic Logic Structure for Data-Path Computation. 22nd ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2014), Monterey, California, 2014.
7. X. Tang, P.-E. Gaillardon and G. De Micheli. Pattern-Based FPGA Logic Block and Clustering Algorithm. 24th International Conference on Field Programmable Logic and Applications (FPL), Munich, Germany, 2014.
8. J. Sandrini, A. Cevrero, T. Demirci, P.-E. Gaillardon and D. Sacchetto et al. Heterogeneous integration of ReRAM crossbars in a CMOS foundry chip. 40th International Micro and Nano Engineering Conference (MNE), Lausanne, Switzerland, 2014.
9. X. Tang, P.-E. Gaillardon and G. De Micheli. A High-Performance Low-Power Near-Vt RRAM-based FPGA. International Conference on Field-Programmable Technology (FPT), Shanghai, China, 2014.
10. J. Zhang, M. De Marchi, P.-E. Gaillardon and G. De Micheli. A Schottky-Barrier Silicon FinFET with 6.0 mV/dec Subthreshold Slope over 5 Decades of Current. International Electron Devices Meeting (IEDM’14), San Francisco, California, USA, 2014.
11. S. Ghoreishizadeh, T. Yalçin, A. Pullini, G. De Micheli and W. Burleson et al. A Lightweight Cryptographic System for Implantable Biosensors. IEEE Biomedical Circuits and Systems Conference (BIOCAS 2014), Lausanne, Switzerland, 2014.
12. S. Ghoreishizadeh, C. Boero, A. Pullini, C. Baj-Rossi and S. Carrara et al. Sub-mW Reconfigurable Interface IC for Electrochemical Sensing. IEEE Biomedical Circuits and Systems Conference (BIOCAS 2014), Lausanne, Switzerland, 2014.
13. A. Zaher, F. Puppo, P. Häfliger, G. De Micheli and S. Carrara. Novel Readout Circuit for Memristive Biosensors in Cancer Detection. IEEE Biomedical Circuits and Systems Conference (BIOCAS 2014), Lausanne, Switzerland, 2014.
14. F. Puppo, M.-A. Doucey, J.-F. Delaloye, T. Moh and G. Pandraud et al. High Sensitive Detection in Tumor Extracts with SiNW-FET in-Air Biosensors. IEEE Sensors 2014, Valencia, Spain, 2014.
15. O. Zografos, L. Amarù, P.-E. Gaillardon and G. De Micheli. Majority Logic Synthesis for Spin Wave Technology. Euromicro Conference on Digital System Design 2014, Verona, Italy, 2014.
16. C. Baj-Rossi, G. De Micheli and S. Carrara. Electrochemical Biochip for Applications to Wireless and Batteryless Monitoring of Free-Moving Mice. 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC 2014), Chicago, Illinois, USA, 2014.
17. F. Puppo, M.-A. Doucey, M. Di Ventra, G. De Micheli and S. Carrara. Memristor-Based Devices for Sensing. IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, Austrailia, 2014.
18. J. M. Ghaye, C. Succa, D. Demarchi, S. K. Muldur and P. Colpo et al. Quantitative Estimation of Biological Cell Surface Receptors by Segmenting Conventional Fluorescence Microscopy Images. 2014 IEEE International Symposium on Circuits and Systems (ISCAS 2014), Melbourne, Australia, 2014.
19. P.-E. Gaillardon, L. Amarù and G. De Micheli. Unlocking Controllable-Polarity Transistors Opportunities by Exclusive-OR and Majority Logic Synthesis. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), Tampa, Florida, 2014.
20. S. Rahimian Omam, Y. Leblebici and G. De Micheli. Parallel vs. Serial Inter-plane communication using TSVs. 5th IEEE Latin American Symposium on Circuits and Systems (LASCAS), Santiago, Chile, 2014.
21. L. Amarù, P.-E. Gaillardon and G. De Micheli. Majority-Inverter Graph: A Novel Data-Structure and Algorithms for Efficient Logic Optimization. 51st Design Automation Conference (DAC), San Francisco, California, USA, 2014.
22. K. Kang, S. Lee, G. De Micheli and C.-M. Kyung. Temperature-Aware Runtime Power Management for Chip-Multiprocessors with 3-D Stacked Cache. International Symposium on Quality Electronic Design (ISQED), Santa Clara, California, USA, 2014.
23. P.-E. Gaillardon, L. Amaru, J. Zhang and G. De Micheli. Advanced System on a Chip Design Based on Controllable-Polarity FETs, (invited). Design, Automation and Test in Europe Conference (DATE), Dresden, Germany, 2014.
24. L. Amarù, P.-E. Gaillardon and G. De Micheli. An Efficient Manipulation Package for Biconditional Binary Decision Diagrams. Design, Automation and Test in Europe (DATE), Dresden, Germany, 2014.
25. L. Amarù, P.-E. Gaillardon, A. Burg and G. De Micheli. Data Compression via Logic Synthesis. 19th Asia and South Pacific Design Automation Conference (ASP-DAC 2014), Singapore, 2014.

2013

1. F. Puppo, M.-A. Doucey, T. S. Y. Moh, G. Pandraud and P. M. Sarro et al. Femto-Molar Sensitive Field Effect Transistor Biosensors Based on Silicon Nanowires and Antibodies. IEEE Sensors, Baltimore, Maryland, USA, 2013.
2. H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, M. Yazdani and G. De Micheli. A Fast TCAD-based Methodology for Variation Analysis of Emerging Nano-Devices. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), New York City, New York, USA, 2013.
3. A. Simalatsar, W. You, D. Sun, V. Gotta and N. Widmer et al. A Control Flow Prototype for a Dose Recommending Device for Chronic Myeloid Leukemia Patients. Medical Cyber Physical Systems Workshop 2013, Philedelphia, Pennsylvania, USA, 2013.
4. S. S. Ghoreishizadeh, N. Gaurav, S. Carrara and G. De Micheli. Empirical Study of Noise Dependence in Electrochemical Sensors. 5th International Workshop on Advances in Sensors and Interfaces (IWASI), Bari, Italy, 2013.
5. S. S. Ghoreishizadeh, S. Carrara and G. De Micheli. A Configurable IC to Control, Readout and Calibrate an Array of Biosensors. 2013 European Conference on Circuit Theory and Design (ECCTD), Dresden, Germany, 2013.
6. C. Gasnier, P.-E. Gaillardon and G. De Micheli. SATSoT: A Methodology to Map Controllable-Polarity Devices on a Regular Fabric Using SAT. IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), Brooklyn, NY, USA, 2013.
7. C. Baj-Rossi, E. Kilinç, S. Ghoreishizadeh, D. Casarino and T. Rezzonico Jost et al. Fabrication and Packaging of a Fully Implantable Biosensor Array. IEEE Biomedical Circuits and Systems Conference (BIOCAS 2013), Rotterdam, the Netherlands, 2013.
8. S. Ghoreishizadeh, E. Kilinc, C. Baj-Rossi, C. Dehollain and S. Carrara et al. An Implantable Bio-Micro-system for Drug Monitoring. IEEE Biomedical Circuits and Systems Conference (BIOCAS 2013), Rotterdam, the Netherlands, 2013.
9. W. You, A. Simalatsar and G. De Micheli. Parameterized SVM for Personalized Drug Concentration Prediction. 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), Osaka, Japan, 2013.
10. G. Koklu, R. Etienne-Cummings, Y. Leblebici, G. D. Micheli and S. Carrara. Characterization of Standard CMOS Compatible Photodiodes and Pixels for Lab-on-Chip Devices. 2013 IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, 2013.
11. L. Amarù, P.-E. Gaillardon and G. De Micheli. Efficient Arithmetic Logic Gates Using Double-Gate Silicon Nanowire FETs, invited paper. 11th IEEE International NEWCAS Conference, Paris, France, 2013.
12. I. Kazi, P. A. Meinerzhagen, P.-E. J. M. Gaillardon, D. Sacchetto and A. P. Burg et al. A ReRAM-Based Non-Volatile Flip-Flop with Sub-VT Read and CMOS Voltage-Compatible Write., 11th IEEE International NEWCAS Conference, Paris, France, 2013.
13. P.-E. Gaillardon, M. De Marchi, L. Amaru, S. Bobba and D. Sacchetto et al. Towards Structured ASICs Using Polarity-Tunable SiNW Transistors, invited. 50th Design Automation Conference (DAC 2013), Austin, Texas, USA, 2013.
14. L. Amaru, P.-E. Gaillardon and G. De Micheli. BDS-MAJ: A BDD-based Logic Synthesis Tool Exploiting Majority Logic Decomposition, 50th Design Automation Conference (DAC 2013), Austin, Texas, USA, 2013.
15. J. Olivo, S. S. Ghoreishizadeh, S. Carrara and G. De Micheli. Electronic Implants: Power Delivery and Management, Design, Automation & Test in Europe Conference (DATE 2013), Grenoble, France, 2013.
16. P.-E. Gaillardon, S. Bobba, L. Amàru, M. De Marchi and D. Sacchetto et al. Vertically Stacked Double Gate Nanowires FETs with Controllable Polarity: From Devices to Regular ASICs, Design, Automation & Test in Europe Conference (DATE 2013), 2013.
17. P.-E. Gaillardon, H. Ghasemzadeh and G. De Micheli. Vertically-Stacked Silicon Nanowire Transistors with Controllable Polarity: a Robustness Study, 14th IEEE Latin American Test Workshop (LATW), Cordoba, Argentina, 2013.
18. S. K. Bobba, P.-E. Gaillardon, C. Seiculescu, V. Pavlidis and G. De Micheli. 3.5-D Integration: A Case Study, IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 2013.
19. O. Türkyilmaz, L. Amarù, F. Clermidy, P.-E. Gaillardon and G. De Micheli. Self-Checking Ripple-Carry Adder with Ambipolar Silicon Nanowire FET, IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 2013.
20. J. Zhang, P.-E. Gaillardon and G. De Micheli. Dual-threshold-voltage configurable circuits with three-independent gate silicon nanowire FETs, IEEE International Symposium on Circuits and Systems (ISCAS), Beijing, China, 2013.
21. L. Amarù, P.-E. Gaillardon and G. De Micheli. Biconditional BDD: A Novel Canonical BDD for Logic Synthesis targeting XOR-rich Functions, Design, Automation & Test in Europe Conference (DATE 2013), Grenoble, France, 2013.
22. L. Amarù, P.-E. Gaillardon and G. De Micheli. MIXSyn: An Efficient Logic Synthesis Methodology for Mixed XOR-AND/OR Dominated Circuits , 18th Asia and South Pacific Design Automation Conference (ASP-DAC 2013), Yokohama, Japan, 2013.
23. J. Jung, K. Kang, G. De Micheli and C.-M. Kyung. Runtime 3-D Stacked Cache Management for Chip-Multiprocessors, The International Symposium on Quality Electronic Design (ISQED 2013), Santa Clara, California, 2013.

2012

1. S. Rahimian, V. F. Pavlidis and G. De Micheli. A Low-Overhead Method for Pre-bond Test of Resonant 3-D Clock Distribution Networks. IEEE 3rd International Worksh op on Testing Three - Dimensional Stacked Integrated Circuits (3D-Test), Anaheim, California, USA, 2012.
2. S. Rahimian, G. De Micheli and V. F. Pavlidis. Low-power clock distribution networks for 3-D ICs. 2012 IEEE 27th Convention of Electrical and Electronics Engineers in Israel, Eilat, Israel, 2012.
3. G. Beanato, I. Loi, G. De Micheli, Y. Leblebici and L. Benini. 3D-LIN: A Configurable Low-Latency Interconnect for Multi-Core Clusters with 3D Stacked L1 Memory. IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Santa Cruz, California, USA, 2012.
4. J. Ghaye, G. De Micheli and S. Carrara. Quantification of Sub-resolution Sized Targets in Cell Fluorescent Imaging. IEEE Biomedical Circuits and Systems Conference (BioCAS 2012), Hsinchu, Taiwan, 2012.
5. S. S. Ghoreishizadeh, I. Taurino, S. Carrara and G. De Micheli. A Current-Mode Potentiostat for Multi-Target Detection Tested with Different Lactate Biosensors. IEEE Biomedical Circuits and Systems Conference (BioCAS 2012), Hsinchu, Taiwan, 2012.
6. A. Cavallini, C. Baj-Rossi, S. Ghoreishizadeh, G. De Micheli and S. Carrara. Design, fabrication, and test of a sensor array for perspective biosensing in chronic pathologies. IEEE Biomedical Circuits and Systems Conference (BioCAS 2012), Hsinchu, Taiwan, 2012.
7. S. Carrara, A. Cavallini, S. Ghoreishizadeh, J. Olivo and G. De Micheli. Developing Highly-Integrated Subcutaneous Biochips for Remote Monitoring of Human Metabolism. IEEE Sensors Conference, Taipei, Taiwan, 2012.
8. K. Kang, L. Benini and G. De Micheli. A High-throughput and Low-Latency Interconnection Network for Multi-Core Clusters with 3-D Stacked L2 Tightly-Coupled Data Memory. IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Santa Cruz, California, USA, 2012.
9. P.-E. Gaillardon, D. Sacchetto, S. Bobba, Y. Leblebici and G. De Micheli. GMS: Generic Memristive Structure for Non-Volatile FPGAs. IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Santa Cruz, California, USA, 2012.
10. M. De Marchi, D. Sacchetto, S. Frache, J. Zhang and P.-E. J. M. Gaillardon, Y. Leblebici and G. De Micheli, Polarity Control in Double-Gate, Gate-All-Around Vertically Stacked Silicon Nanowire FETs, International Electron Devices Meeting (IEDM), San Francisco, California, USA, 2012.
11. A. Simalatsar and G. De Micheli, Medical Guidelines Reconciling Medical Software and Electronic Devices: Imatinib Case-study, IEEE 12th International Conference on BioInformatics and BioEngineering (BIBE'12), Larnaca, Cyprus, 2012.
12. C. Seiculescu, L. Benini and G. De Micheli. A Distributed Interleaving Scheme for Efficient Access to Wide IO DRAM Memory, International Conference on Hardware/Software Codesign and System Synthesis (CODES + ISSS), Tampere, Finland, 2012.
13. W. You, A. Simalatsar, N. Widmer and G. De Micheli, A Drug Administration Decision Support System, IEEE International Conference on Bioinformatics and Biomedicine (BIBM), Philadelphia, Pennsylvania, USA, 2012.
14. W. You, A. Simalatsar and G. De Micheli, RANSAC-based Enhancement in Drug Concentration Prediction Using Support Vector Machine, International Workshop on Innovative Simulation for Healthcare (IWISH), Vienna, Austria, 2012.
15. V. Pavlidis, H. Xu and G. De Micheli. Enhanced Wafer Matching Heuristics for 3-D ICs, IEEE 17th European Test Symposium, Annecy, France, 2012.
16. S. Bobba, P.-E. J. M. Gaillardon, J. Zhang, M. De Marchi and D. Sacchetto et al. Process/Design Co-optimization of Regular Logic Tiles for Double-Gate Silicon Nanowire Transistors, IEEE /ACM International Symposium on Nanoscale Architectures (NANOARCH '12), Amsterdam, Netherlands, 2012.
17. A. Simalatsar and G. De Micheli. TAT-based Formal Representation of Medical Guidelines : Imatinib Case-study, 34th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC 2012), San Diego, California, USA, 2012.
18. J. Olivo, S. Carrara and G. De Micheli. IronIC Patch: A Wearable Device for the Remote Powering and Connectivity of Implantable Systems, IEEE International Instrumentation and Measurement Technology Conference (I2MTC 2012), Graz, Austria, 2012.
19. G. De Micheli, C. Boero, C. Baj-Rossi, I. Taurino and S. Carrara. Integrated Biosensors for Personalized Medicine, 49th Design Automation Conference (DAC), San Francisco, California, USA, 2012.
20. G. Köklü, J. M. Ghaye, R. Beuchat, G. De Micheli and Y. Leblebici et al. Quantitative Comparison of Commercial CCD and Custom-Designed CMOS Camera for Biological Applications, 2012 IEEE International Symposium on Circuits and Systems (ISCAS 2012), Seoul, Korea, 2012.
21. S. Bobba, M. De Marchi, Y. Leblebici and G. De Micheli. Physical Synthesis onto Sea-of-Tiles with Double-Gate Silicon Nanowire Transistors, 49th Design Automation Conference (DAC), San Francisco, California, USA, 2012.
22. H. Xu, V. Pavlidis, W. Burleson and G. De Micheli. The Combined Effect of Process Variations and Power Supply Noise on Clock Skew and Jitter, IEEE International Symposium on Quality Electronic Design (ISQED), Santa Clara, California, USA, 2012.
23. G. De Micheli. Engineering Complex Systems for Health, Security and the Environment, 17th Asia and South Pacific Design Automation Conference, Sydney, Australia, 2012.
24. C. Zhang, V. Pavlidis and G. De Micheli. Voltage Propagation Method for 3-D Power Grid Analysis, Design, Automation and Test in Europe (DATE'12), Dresden, Germany, 2012.
25. S. Volos, C. Seiculescu, B. Grot, N. Khosro Pour and B. Falsafi et al. CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers, 6th International Symposium on Networks-on-Chip, Lyngby, Denmark, 2012.

2011

1. C. Boero, S. Carrara and G. De Micheli. New Technologies for Nanobiosensing and their Applications to Real-Time Monitoring. IEEE Biomedical Circuits and Systems Conference (BioCAS 2011), San Diego, California, USA, 2011.
2. G. De Micheli. Integrated biosensing for diagnosis and therapy. 4th Annual World Congress of Industrial Biotechnology (ibio-2011), Dalian, China, 2011.
3. H. Xu, V. Pavlidis and G. De Micheli. Skew Variability in 3-D ICs with Multiple Clock Domains. IEEE International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, 2011.
4. S. Rahimian Omam, V. Pavlidis and G. De Micheli. Design of Resonant Clock Distribution Networks for 3-D Integrated Circuits. 21st International Conference on Integrated Circuit and System Design: Power and Timing, Modeling, Optimization, and Simulation (PATMOS'11), Madrid, Spain 2011.
5. F. Zanini, D. Atienza Alonso and G. De Micheli. Convex-Based Thermal Management for 3D MPSoCs Using DVFS and Variable-Flow Liquid Cooling. 21st International Conference on Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation (PATMOS'11), Madrid, Spain, 2011.
6. P. Batude, M. Vinet, B. Previtali, C. Tabone, C. Xu, J. Mazurier, O. Weber, F. Andrieu, L. Tosti, L. Brevard, B. Sklenard, B. Coudrain, S.K. Bobba, H. Ben Jamaa, P.-E. Gaillardon, A. Pouydebasque, O. Thomas, C. Le Royer, J.-M. Hartmann, L. Sanchez, L. Baud, V. Carron, L. Clavelier, G. De Micheli, S. Deleonibus, O. Faynot and T. Poiroux, Advances, Challenges and Opportunities in 3D CMOS Sequential Integration. IEEE International Electron Devices Meeting (IEDM), Washington DC, USA, 2011.
7. D. Sacchetto, M. De Marchi, G. De Micheli and Y. Leblebici. Alternative Design Methodologies for the Next Generation Logic Switch (invited paper). International Conference on Computer-Aided Design (ICCAD), San Jose, California, USA, 2011.
8. W. You, N. Widmer and G. De Micheli. Personalized Modeling for Drug Concentration Prediction Using Support Vector Machine. 4th International Conference on Biomedical Engineering and Informatics (BMEI), Shanghai, China, 2011.
9. S. Carrara, L. Bolomey, C. Boero, A. Cavallini, E. Meurville, G. De Micheli, T. Rezzonico, M. Proietti and F. Grassi, Single-Metabolite Bio-Nano-Sensors and System for Remote Monitoring in Animal Models. IEEE Sensors Conference, Limerick, Ireland, 2011.
10. W. You, N. Widmer and G. De Micheli. Example-based Support Vector Machine for Drug Concentration Analysis. 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC 2011), Boston, Massachusetts, USA, 2011.
11. J. Joven Murillo, P. Strid, D. Castells-Rufas, A. Bagdia, G. De Micheli and J. Carrabina, HW-SW Implementation of a Decoupled FPU for ARM-based Cortex-M1 SoCs in FPGAs. 6th IEEE International Symposium on Industrial Embedded Systems (SIES'11), Vasteras, Sweden, 2011.
12. M. Beltrandi, A. Vachoux, S. Carrara, Y. Leblebici and G. De Micheli. VHDL-AMS Model of an Electrochemical Cell to Design VLSI Bio-Chips. IEEE Biomedical Circuits and Systems Conference (BioCAS), San Diego, California, USA, 2011.
13. D. Sacchetto, S. Xie, A. V. Savu, M. Zervas, G. De Micheli, J. Brugger and Y. Leblebici, Vertically-Stacked Si Nanowire FETs with sub-micrometer Gate-All-Around polysilicon gates patterned by nanostencil lithography. 37th International Conference on Micro and Nano Engineering (MNE), Berlin, Germany, 2011.
14. C. Seiculescu, S. Volos, N. Khosro Pour, B. Falsafi and G. De Micheli. CCNoC: On-Chip Interconnects for Cache-Coherent Manycore Server Chips. Workshop on Energy-Efficient Design (WEED 2011), San Jose, California, USA, 2011.
15. C. Seiculescu, S. Murali, L. Benini and G. De Micheli. A DRAM Centric NoC Architecture and Topology Design Approach. IEEE Computer Society Annual Symposium on VLSI, Chennai, India, 2011.
16. I. Taurino, S. Carrara, M. Giorcelli, A. Tagliaferro and G. De Micheli. Comparing the enhanced sensing interfaces of differently oriented carbon nanotubes onto silicon for bio-chip applications. 4th International Workshop on Advances in Sensors and Interfaces (IWASI), Savelletri di Fasaro, Brindisi, Italy, 2011.
17. G. De Micheli, V. Pavlidis, D. Atienza Alonso and Y. Leblebici. Design Methods and Tools for 3D Integration. Symposium on VLSI Technology, Kyoto, Japan, 2011.
18. D. Sacchetto, G. De Micheli and Y. Leblebici. Ambipolar Si Nanowire Field Effect Transistors for Low Current and Temperature Sensing. 16th International Conference on Solid-State Sensors, Actuators and Microsystems, Beijing, China, 2011.
19. S. S. Ghoreishizadeh, C. Baj-Rossi, S. Carrara and G. De Micheli. Nano-Sensor and Circuit Design for Anti-Cancer Drug Detection. IEEE/NIH 5th Life Science Systems and Applications Workshop, Bethesda, Maryland, USA, 2011.
20. J. Olivo, S. Carrara and G. De Micheli. Modeling of Printed Spiral Inductors for Remote Powering of Implantable Biosensors. 5th International Symposium on Medical Information and Communication Technology, Montreux, Switzerland, 2011.
21. S. K. Bobba, A. Chakraborty, O. Thomas, P. Batude, T. Ernst, O. Faynot, D.Z. Pan and G. De Micheli, CELONCEL: Effective Design Technique for 3-D Monolithic Integration targeting High Performance Integrated Circuits. 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), Yokohama, Japan, 2011.
22. F. Zanini, D. Atienza Alonso, L. Benini and G. De Micheli. Thermal-Aware System-Level Modeling and Management for Multi-Processor Systems-on-Chip. IEEE International Symposium on Circuits and Systems (ISCAS), Rio de Janeiro, Brazil, 2011.
23. G. De Micheli. Logic Synthesis and Physical Design: Quo Vadis. Design, Automation and Test in Europe (DATE 2011), Grenoble, France, 2011.
24. H. Xu, V. F. Pavlidis and G. De Micheli. Analytical Heat Transfer Model for Thermal Through-Silicon Vias. Design, Automation and Test in Europe (DATE 2011), Grenoble, France, 2011.
25. G. De Micheli, S. S. Ghoreishizadeh, C. Boero, F. Valgimigli and S. Carrara. An Integrated Platform for Advanced Diagnostics. Design, Automation and Test in Europe (DATE 2011), Grenoble, France, 2011.

2010

1. M. Lombardi, L. Benini, A. Garg and G. De Micheli. Methods for Designing Reliable Probe Arrays. IEEE International Conference on BioInformatics and BioEngineering (BIBE), Philadelphia, Pennsylvania, 2010.
2. D. Sacchetto, V. Savu, G. De Micheli, J. Brugger and Y. Leblebici. Ambipolar silicon nanowire FETs with stenciled sub-μm metal gate, 36th International Conference on Micro and Nano Engineering (MNE 2010), Genova, Italy, 2010.
3. V. Pavlidis, H. Xu, I. Tsioutsios, and G. De Micheli, Synchronization and Power Integrity Issues in 3-D ICs, in Proceedings of Asia Pacific Conference on Circuits and Systems, Kuala Lumpur, Malaysia, pp. 536-539, 2010.
4. I. Tsioutsios, V. Pavlidis, and G. De Micheli, Physical Design Tradeoffs in Power Distribution Networks for 3-D ICs, in Proceedings of the 17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2010), Athens, Greece, pp. 435-438, 2010.
5. M. De Marchi, S. Bobba, H. Ben Jamaa, and G. De Micheli, Synthesis of regular computational fabrics with ambipolar CNTFET technology, in Proceedings of the 17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2010), Athens, Greece, 2010.
6. J. Joven, F. Angiolini, D. Castells-Rufas, G. De Micheli, and J. Carrabina, QoS-ocMPI: QoS-aware on-chip Message Passing Library for NoC-based Many-Core MPSoCs, in Proceedings of the 2nd Workshop on Programming Models for Emerging Architectures (PMEA'10), Vienna, Austria, pp. 65-74, 2010.
7. J. Joven Murillo, A. Marongiu, F. Angiolini, L. Benini, and G. De Micheli, Exploring Programming Model-driven QoS Support for NoC-based Platforms, in Proceedings of International Conference on Hardware/Software Codesign and System Synthesis (CODES+ ISSS'10), Sottsdale, Arizona, USA, 2010.
8. S. K. Bobba, A. Chakraborthy, O. Thomas, P. Batude, V. Pavlidis, and G. De Micheli, Performance Analysis of 3-D Monolithic Integrated Circuits, in Proceedings of the IEEE International 3D System Integration Conference (3DIC'10), Munich, Germany, 2010.
9. S. Carrara, M. D. Torre, A. Cavallini, D. De Venuto, and G. De Micheli, Multiplexing pH and Temperature in a Molecular Biosensor, in Proceedings of the IEEE BIOCAS Conference, Paphos, Cyprus, 2010.
10. D. De Venuto, M. D. Torre, C. Boero, S. Carrara, and G. De Micheli, A Novel Multi-Working Electrode Potentiostat for Electrochemical Detection of Metabolites, in Proceedings of the IEEE Sensors Conference, Waikoloa, Hawaii, USA, vol. 1, pp. 1572-1577, 2010.
11. J. Olivo, S. Carrara, and G. De Micheli, Optimal Frequencies for Inductive Powering of Fully Implantable Biosensors for Chronic and Elderly Patients, in Proceedings of the IEEE Sensors Conference, Waikoloa, Hawaii, USA, vol. 1, pp. 99-103, 2010.
12. A. Cavallini, S. Carrara, G. De Micheli, and V. Erokhin, P450-mediated electrochemical sensing of drugs in human plasma for personalized therapy, in Proceedings of the Conference on PhD Research in Microelectronics and Electronics (PRIME), Berlin, Germany, 2010.
13. A. Biyabani, C. Guiducci, and G. De Micheli, Regenerative Circuits for Rapid Biosensing, in 17th IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Athens, Greece, 2010.
14. C. Boero, S. Carrara, G. Del Vecchio, G. D. Albini, L. Calzà, and G. De Micheli, Carbon Nanotubes-Based Electrochemical Sensing for Cell Culture Monitoring, in Proceedings of the 2010 IEEE/ICME International Conference on Complex Medical Engineering, Gold Coast, Australia, vol. 1, pp. 288-293, 2010.
15. M. De Marchi, H. Ben Jamaa, and G. De Micheli, Regular Fabric Design with Ambipolar CNTFETs for FPGA and Structured ASIC Applications, in IEEE/ACM International Symposium on Nanoscale Architectures (Nanoarch'10), Anaheim, California, USA, 2010.
16. H. Xu, V. F. Pavlidis, and G. De Micheli, Process-induced skew variation for scaled 2-D and 3-D ICs, in Proceedings of the 12th ACM/IEEE International Workshop on System Level Interconnect Prediction - SLIP '10, pp. 17-24, Anaheim, California, USA, 2010.
17. J. Zhang, S. Bobba, N. Patil, A. Lin, H.-S. P. Wong, G. De Micheli, and S. Mitra, Carbon Nanotube Correlation: Promising Opportunity for CNFET Circuit Yield Enhancement, in Proceedings of the 47th Design Automation Conference (DAC 2010), Anaheim, California, USA, vol. 1, pp. 889-892, 2010.
18. G. De Micheli, C. Seiculescu, S. Murali, L. Benini, F. Angiolini, and A. Pullini, Networks on Chips: from Research to Products, in Proceedings of the 47th Design Automation Conference (DAC 2010), Anaheim, California, USA, vol. 1, pp. 300-305, 2010.
19. D. Sacchetto, H. Ben-Jamaa, S. Carrara, G. De Micheli, and Y. Leblebici, Memristive Devices Fabricated with Silicon Nanowire Schottky Barrier Transistors, in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2010), Paris, France, vol. 1, pp. 9-12, 2010.
20. D. Sacchetto, H. Ben-Jamaa, G. De Micheli, and Y. Leblebici, Design Aspects of Carry Lookahead Adders with Vertically-Stacked Nanowire Transistors, in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2010), Paris, France, vol. 1, pp. 1715-1717, 2010.
21. H. Ben Jamaa, K. Mohanram, and G. De Micheli, Power Consumption of Logic Circuits in Ambipolar Carbon Nanotube Technology, in Proceedings of the Design, Automation and Test in Europe (DATE), Dresden, Germany, 2010.
22. F. Zanini, D. Atienza Alonso, G. De Micheli, and S. P. Boyd, Online Convex Optimization-Based Algorithm for Thermal Management of MPSoCs, in Proceedings of the 20th ACM Great Lakes Symposium on VLSI (GLSVLSI 2010), Providence, Rhode Island, USA, vol. 1, pp. 203-208, 2010.
23. C. Seiculescu, S. Murali, L. Benini, and G. De Micheli, A Method to Remove Deadlocks in Networks-on-Chips with Wormhole Flow Control, in Proceedings of the Design, Automation and Test in Europe (DATE), Dresden, Germany, 2010.
24. F. Zanini, D. Atienza, C. N. Jones, and G. De Micheli, Temperature Sensor Placement in Thermal Management Systems for MPSoCs, in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2010), Paris, France, vol. 1, pp. 1065-1068, 2010.
25. F. Zanini, C. N. Jones, D. Atienza, and G. De Micheli, Multicore Thermal Management using Approximate Explicit Model Predictive Control, in Proceedings of the of IEEE International Symposium on Circuits and Systems (ISCAS 2010), Paris, France, vol. 1, pp. 3321-3324, 2010.
26. S. Bobba, S. Carrara, and G. De Micheli, Design of a CNFET Array for Sensing and Control in P450 based Biochips for multiple drug detection, in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2010), Paris, France, vol. 1, pp. 1065-1068, 2010.
27. N. Archontas, J. Georgiou, H. Ben Jamaa, S. Carrara, and G. De Micheli, Characterization of Memristive Poly-Si Nanowires via Empirical Physical Modelling, in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 2010), Paris, France, vol. 1, pp. 1675-1678, 2010.

2009

1. A. Garg, K. Mohanram, A. Di Cara, G. De Micheli, and I. Xenarios, Modeling stochasticity and robustness in gene regulatory networks, in Joint Conference of Intelligent Systems for Molecular Biology (ISMB)/8th European Conference on Computational Biology (ECCB), Stockholm, Sweden, (Bioinformatics, vol. 25, no. 12, pp. i101-i109), 2009.
2. G. De Micheli, Nano-Tera.CH: Nano-technologies for Tera-scale Problems, in Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting, Capri, Italy, 2009.
3. C. Boero, S. Carrara, and G. De Micheli, Amperometric biosensor with nanostructured electrodes by using multi-alled carbon nanotubes for glucose detection in cell culture medium, in NanoTech 2009, Montreux, Switzerland, 2009.
4. H. Xu, V. F. Pavlidis, and G. De Micheli, Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits, in Nano-Net 2009, Luzern, Switzerland, 2009.
5. A. V. Sathanur, A. Pullini, L. Benini, G. De Micheli, and E. Macii, Physically clustered forward body biasing for variability compensation in nanometer CMOS design, in Design, Automation and Test in Europe Conference (DATE), Dresden, Germany, 2009.
6. D. Rahmati, S. Murali, L. Benini, F. Angiolini, G. De Micheli, and H. Sarbazi-Azad, A Method for Calculating Hard QoS Guarantees for Networks-on-Chip, in Proceedings of the International Conference on CAD (ICCAD), San Jose, California, USA, 2009.
7. S. Carrara, C. Boero, and G. De Micheli, Quantum Dots and Wires to Improve Enzymes-Based Electrochemical Bio- sensing, in Nano-Net 2009, Luzern, Switzerland, 2009.
8. S. Carrara, A. Cavallini, Y. Leblebici, G. De Micheli, V. Bhalla, F. Valle, B. Samori, L. Benini, B. Ricco, V. Vikholm-Lundin, and T. Munter, New probe immobilizations by lipoate-diethalonamine or ethylene-glycol molecules for capacitance DNA chip, in 3rd IEEE International Workshop on Advances in Sensors and Interfaces (IWASI), Trani, Italy, pp. 9-14, 2009.
9. C. Boero, S. Carrara, and G. De Micheli, Sensitivity Enhancement by Carbon Nanotubes: Applications to Stem Cell Cultures Monitoring, in 5th International Conference on Ph.D. Research in Microelectronics & Electronics (PRIME), Cork, Ireland, pp. 260-263, 2009.
10. S. Carrara, A. Cavallini, A. Garg, and G. De Micheli, Dynamical Spot Queries to Improve Specificity in P450s based Multi-Drugs Monitoring, in IEEE/ICME International Conference on Complex Medical Engineering, Tempe, Arizona, USA, 2009.
11. D. Sacchetto, M. H. Ben Jamaa, G. De Micheli, and Y. Leblebici, Fabrication and Characterization of Vertically Stacked Gate-All-Around Si Nanowire FET Arrays, in 39th European Solid-State Device Research Conference (ESSDERC), Athens, Greece, 2009.
12. M. H. Ben Jamaa, S. Carrara, J. Georgiou, N. Archontas, and G. De Micheli, Fabrication of Memristors with Poly-Crystalline Silicon Nanowires, in 9th Nanotechnology Conference (IEEE Nano), Genoa, Italy, 2009.
13. M. H. Ben Jamaa, G. Cerofolini, Y. Leblebici, and G. De Micheli, Complete Nanowire Crossbar Framework Optimized for the Multi-Spacer Patterning Technique, in International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), Grenoble, France, 2009.
14. V. F. Pavlidis and G. De Micheli, Power Distribution Paths for 3-D IC, in ACM Great Lakes Symposium on VLSI (GLSVLSI 2009), Boston, Massachusetts, 2009.
15. I. Savidis, V. F. Pavlidis, E. G. Friedman, and G. De Micheli, Clock and Power Distribution Networks for 3-D ICs, in ACM/IEEE Conference on Design, Automation, and Test in Europe (DATE), Nice, France, 2009.
16. H. Ben Jamaa, Y. Leblebici, and G. De Micheli, Decoding Nanowire Arrays Fabricated with the Multi-Spacer Patterning Technique, in 46th Design Automation Conference (DAC), San Francisco, California, 2009.
17. C. Seiculescu, S. Murali, L. Benini, and G. De Micheli, NoC Topology Synthesis for Supporting Shutdown of Voltage Islands in SoCs, in 46th Design Automation Conference (DAC), San Francisco, California, pp. 822-825, 2009.
18. B. Ben Jamaa, K. Mohanram, and G. De Micheli, Novel Library of Logic Gates with Ambipolar CNTFETs: Opportunities for Multi-Level Logic Synthesis, in Design, Automation and Test in Europe (DATE), Nice, France, pp. 622-627, 2009.
19. F. Zanini, D. Atienza, L. Benini, and G. De Micheli, Multicore Thermal Management with Model Predictive Control, in Proceedings of the IEEE 19th European Conference on Circuit Theory and Design (ECCTD), Antalya, Turkey, vol. 1, pp. 90-95, 2009.
20. F. Zanini, D. Atienza, A. K. Coskun, and G. De Micheli, Optimal Multi-Processor SoC Thermal Simulation via Adaptive Differential Equation Solvers, in Proceedings of the 17th Annual IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Florianopolis, Brazil, vol. 1, pp. 80-85, 2009.
21. F. Zanini, D. Atienza, and G. De Micheli, A Control Theory Approach for Thermal Balancing of MPSoC, in Proceedings of the IEEE/ACM 14th Asia and South Pacific Design Automation Conference, Yokohama, Japan, vol. 1, pp. 7-12, 2009.
22. C. Seiculescu, S. Murali, L. Benini, and G. De Micheli, SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3D Systems on Chip, in Design, Automation and Test in Europe (DATE), Nice, France, pp. 9-14, 2009.
23. S. Murali, C. Seiculescu, L. Benini, and G. De Micheli, Synthesis of Networks on Chips for 3D Systems on Chips, in Proceedings of the IEEE/ACM Asia and South Pacific Design Automation Conference, (ASPDAC), Yokohama, Japan, pp. 242-247, 2009.
24. E. D. N. Ndih, N. Khaled, and G. De Micheli, An Analytical Model for the Contention Access Period of the Slotted IEEE 802.15.4 with Service Differentiation, in IEEE International Conference on Communication (ICC), Dresden, Germany, pp. 1-6, 2009.
25. F. J. Rincon, L. Gutierrez, M. Jimenez, V. Diaz, N. Khaled, D. Atienza, M. Sanchez-Elez, J. Recas, and G. De Micheli, Implementation of an automated ECG-based diagnosis for a wireless body sensor platform, in Proceedings of the International Conference on Biomedical Electronics and Devices (BIODEVICES), Porto, Portugal, vol. 1, pp. 88-96, Springer, 2009.
26. S. Bobba, J. Zhang, A. Pullini, D. Atienza, H.-S. P. Wong, and G. De Micheli, Design of Compact Imperfection-Immune CNFET Layouts for Standard-Cell-Based Logic Synthesis, in Design, Automation & Test in Europe (DATE 09), Nice, France, pp. 616-621, 2009.
27. M. H. Ben Jamaa, D. Atienza, Y. Leblebici, and G. De Micheli, A Stochastic Perturbative Approach to Design a Defect-Aware Thresholder in the Sense Amplifier of Crossbar Memories, in 14th IEEE/ACM Asia and South Pacific Design Automation Conference, Yokohama, Japan, vol. 1, pp. 835-840, 2009.

2008

1. A. Garg, D. Banerjee, and G. De Micheli, Implicit Methods for Probabilistic Modeling of Gene Reglatory Networks, in 30th IEEE EMBS Annual International Conference 2008, Vancouver, Canada, 2008.
2. V. Rana, D. Atienza, M. D. Santambrogio, D. Sciuto, and G. De Micheli, A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication, in 16th IFIP/IEEE International Conference on Very Large Scale Integration, Rhodes, Greece, pp. 321-326, 2008.
3. S. Carrara, A. Cavallini, G. De Micheli, J. Olivo, L. Benini, V. V. Shumyantseva, and A. I. Arhakov, Circuits Design and Nano-Structured Electrodes for Drugs Monitoring in Personalized Therapy, in Proceedings of IEEE Biomedical Circuits and Systems Conferene (BioCAS), Baltimore, Maryland, USA, 2008.
4. H. Ben Jamaa, D. Atienza, Y. Leblebici, and G. De Micheli, Programmable Logic Circuits based on Ambipolar CNFET, in 45th Design Automation Conference (DAC), Anaheim, California, USA, 2008.
5. Y. Temiz, F. K. Gurkaynak, S. Terrettaz, H. Vogel, G. De Micheli, Y. Leblebici, C. Guiducci, and L. Benini, Real-Time High-Sensitivity Impedance Measurement Interface for Tethered BLM Biosensor Arrays, in Proceedings of the 7th IEEE Sensors Conference, Lecce, Italy, pp. 650-653, 2008.
6. A. Susu, A. Acquaviva, D. Atienza Alonso, and A. De Micheli, Stochastic Modeling and Analysis for Environmentally Powered Wireless Sensor Nodes, in 6th International Symposium on Modeling and Optimization in Mobile, Ad Hoc, and Wireless Networks (WiOPT), Berlin, Germany, vol. 1, pp. 125-134, 2008.
7. D. Atienza, G. De Micheli, L. Benini, J. Ayala, P. Del Valle, M. DeBole, and V. Narayanan, Reliability-Aware Design for Nanometer-Scale Devices, in Asia and South Pacific Design Automation Conference (ASP-DAC), Seoul, Korea, 2008.
8. F. Rincón, M. Paselli, J. Recas, Q. Zhao, M. Sanchez-Elez, D. Atienza, J. Penders, and G. De Micheli, OS-Based Sensor Node Platform and Energy Estimation Model for Health-Care Wireless Sensor Networks, in Design, Automation and Test in Europe (DATE), no. ISSN: 1530-1591/05, Munich, Germany, 2008.
9. F. Mulas, M. Buttu, M. Pittau, S. Carta, D. Atienza, A. Acquaviva, L. Benini, and G. De Micheli, Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures, in Design, Automation and Test in Europe (DATE '08), Munich, Germany, 2008.
10. S. Murali, D. Atienza, L. Benini, and G. De Micheli, Temperature Control of High Performance Multicore Platforms Using Convex Optimization, in Design, Automation and Test in Europe (DATE '08), Munich, Germany, 2008.

2007

1. D. Atienza, S. K. Bobba, M. Poli, G. De Micheli, and L. Benini, System-Level Design for Nano-Electronics, in Proceedings of the 14th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Marrakech, Morocco, vol. 1, pp. 747-751, 2007.
2. A. Garg, I. Xenarios, L. Mendoza, and G. De Micheli, An Efficient Method for Dynamic Analysis of Gene Regulatory Networks and in silico Gene Perturbation Experiments, in 11th Annunal International Conference on Research in Computational Molecular Biology (RECOMB), San Francisco, California, Lecture Notes in Computer Science, Springer, 2007.
3. A. Garg, L. Mendoza, I. Xenarios, and G. De Micheli, Modeling of Multiple Valued Gene Regulatory Networks, in 29th Annual International Conference of the IEEE EMBS, vol. IEEE CNS, Lyon, France, pp. 1398 - 1404, 2007.
4. S. Murali, A. Mutapcic, D. Atienza, R. Gupta, S. P. Boyd, and G. De Micheli, Temperature-Aware Processor Frequency Assignment for MPSoCs Using Convex Optimization, in International Conference on Hardware/Software Codesign and System Synthesis(CODES+ISSS), Salzburg, Austria, ISBN: 978-1-59593-824-4/07/0009, pp. 111-116, 2007.
5. F. J. Rincón, A. E. Susu, M. Sánchez-Élez, D. Atienza, and G. De Micheli, A Simulation Model for Wireless Sensor Networks Based on TOSSIM, in XXII Conference on Design of Circuits and Integrated Systems (DCIS), Sevilla, Spain, ISBN: 978-84690-86929-2, pp. 278-283, IMSE, 2007.
6. P. G. Del Valle, D. Atienza, G. Paci, F. Poletti, L. Benini, G. De Micheli, J. M. Mendias, and R. Hermida, Application of FPGA Emulation to SoC Floorplan and Packaging Exploration, in XXII Conference on Design of Circuits and Integrated Systems (DCIS), Sevilla, Spain, ISBN: 978-84690-86929-2, pp. 236-240, IMSE, 2007.
7. A. Pullini, F. Angiolini, P. Meloni, D. Atienza, S. Murali, L. Raffo, G. De Micheli, and L. Benini, NoC Design and Implementation in 65 nm Technology, in Proceedings of the First International Symposium on Networks-on-Chip (NOCS'07), Princeton, New Jersey, USA, IEEE Circuits and Systems Society, pp. 273-282, 2007.
8. H. Ben Jamaa, K. Moselund, D. Atienza, D. Bouvet, A. Ionescu, Y. Leblebici, and G. De Micheli, Fault-Tolerant Multi-Level Logic Decoder for Nanoscale Crossbar Memory Arrays, in Proceedings of the International Conference on Computer-Aided Design (ICCAD), San Jose, California, USA, pp. 765-772, 2007.
9. F. Angiolini, H. Ben Jamaa, D. Atienza, L. Benini, and G. De Micheli, Improving the Fault Tolerance of Nanometric PLA Designs, in Proceedings of Design Automation and Test in Europe (DATE), Nice, France, ISBN: 978-3-9810801-2-4, pp. 570-575, 2007.
10. P. Raghavan, J. L. Ayala, D. Atienza, F. Catthoor, G. De Micheli, and M. Lopez-Vallejo, Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors, in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS 2007), New Orleans, Loisiana, USA, ISBN: 1-4244-0921-7, pp. 121-124, 2007.
11. S. Carta, A. Acquaviva, P. G. Del Valle, M. Pittau, D. Atienza, F. Rincon, G. De Micheli, L. Benini, and J. M. Mendias, Multi-Processor Operating System Emulation Framework with Thermal Feedback for Systems-on-Chip, in Proceedings of 17th ACM Great Lakes Symposium on VLSI (GLSVLSI), Stresa-Lago Maggiore, Italy, pp. 311-316, 2007.
12. I. Hatirnaz, S. Badel, N. Pazos, Y. Leblebici, S. Murali, D. Atienza, and G. De Micheli, Early Wire Characterization for Predictable Network-on-Chip Global Interconnects, in Proceedings of the 2007 International Workshop on System Level Interconnect Prediction (SLIP), Austin, Texas, USA, pp. 57-64, ACM Press New York, 2007.

2006

1. S. Yoon, A. Garg, E.-Y. Chung, H. S. Park, W. Y. Park, and G. De Micheli, Exploiting Binary Abstractions in Deciphering Gene Interactions, in 28th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBS '06) , New York City, New York, USA, pp. 5858-5863, 2006.
2. D. Atienza, S. Murali, F. Angiolini, L. Benini, G. De Micheli, J. Mendias, and R. Hermida, Diseño de redes en chip de propósito específico con información de rutado físico, in Proceedings of XVII Jornadas de Parelelismo, Albacete, Spain, pp. 597-602, 2006.
3. P. Del Valle, D. Atienza, I. Magan, J. Flores, E. Perez, J. Mendias, L. Benini, and G. De Micheli, Architectural Exploration of MPSoC Designs Based on an FPGA Emulation Framework, in Proceedings of XXI Conference on Design of Circuits and Integrated Systems (DCIS), Barcelona, Spain, pp. 12-18, 2006.
4. P. Del Valle, D. Atienza, I. Magan, J. Flores, E. Perez, J. Mendias, L. Benini, and G. De Micheli, A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework, in Proceedings of 14th Annual IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Nice, France, pp. 140-145, 2006.
5. S. Murali, D. Atienza, L. Benini, and G. De Micheli, A Multi-Path Routing Strategy with Guaranteed In-order Packet Delivery and Fault Tolerance for Networks on Chips, in Proceedings of Design Automation Conference (DAC), San Francisco, California, USA, pp. 845-848, 2006.
6. P. Meloni, S. Murali, S. Carta, M. Camplani, L. Raffo, and G. De Micheli, Routing Aware Switch Hardware Customization for Networks on Chips, in Nano-Networks 2006, Lausanne, Switzerland, 2006.
7. F. Angiolini, D. Atienza, S. Murali, L. Benini, and G. De Micheli, Reliability Support for On-chip Memories Using Networks-on-Chips, in 24th International Conference on Computer Design (ICCD), San Jose, California, USA, pp. 296-306, 2006.
8. S. Murali, P. Meloni, F. Angiolini, D. Atienza, S. Carta, L. Benini, G. De Micheli, and L. Raffo, Designing Application-Specific Networks on Chips with Floorplan Information, in Proceedings of the 2006 International Conference on Computer-Aided Design (ICCAD), San Jose, California, USA, pp. 355-362, 2006.
9. S. Murali, P. Meloni, F. Angiolini, D. Atienza, S. Carta, L. Benini, G. De Micheli, and L. Raffo, Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips, in Proceedings of IFIP International Conference on Very Large Scale Integration (VLSI-SoC), Nice, France, pp. 158-163, 2006.
10. S. Murali, M. Coenen, A. Radulescu, K. Goossens, and G. De Micheli, A Methodology for Mapping Multiple Use-Cases onto Networks on Chips, in Design, Automation and Test in Europe (DATE), Munich, Germany, pp. 118-123, 2006.
11. M. Coenen, S. Murali, A. Radulescu, K. Goossens, and G. De Micheli, A buffer-sizing Algorithm for Networks on Chip using TDMA and credit-based end-to-end Flow Control, in International Conference on Hardware/Software Codes and System Synthesis (CODES+ISSS), Seoul, Korea, 2006.
12. S. Murali, R. Tamhankar, F. Angiolini, A. Pullini, D. Atienza, L. Benini, and G. De Micheli, Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips, in Proceedings of the International Symposium on System-on-Chip, Tampere, Finland, 2006.
13. D. Atienza, P. Raghavan, J. Ayala, G. De Micheli, F. Catthoor, D. Verkest, and M. Lopez-Vallejo, Compiler-Driven Leakage Energy Reduction in Banked Register Files, in Power and Timing Modelling, Optimization and Simulation (PATMOS), Montpellier, France, Springer, Lecture Notes in Computer Science (LNCS) 4148, pp. 107-116, 2006.
14. D. Atienza, P. Garcia Del Valle, G. Paci, F. Poletti, L. Benini, G. De Micheli, and J. Mendias, A Fast HW/SW FPGABased Thermal Emulation Framework for MultiProcessor SystemonChip, in Design Automation Conference (DAC), San Francisco, California, USA, pp. 618-623, 2006.
15. E. Ficarra, E. Macii, G. De Micheli, and L. Benini, Computer-aided evaluation of protein expression in athological tissue images, in 19th IEEE International Symposium on Computer-Based Medical Systems (CBMS), Salt Lake City, Utah, USA, pp. 413 - 418, 2006.
16. I. Folcarelli, T. Kluther, A. E. Susu, A. Acquaviva, and G. De Micheli, An Opportunistic Reconfiguration Strategy for Environmentally Powered Devices, in ACM International Conference on Computing Frontiers, Ischia, Italy, pp. 171-176, 2006.
17. C. Nardini, D. Masotti, S. Yoon, E. Macii, M. D. Kuo, G. De Micheli, and L. Benini, Mining gene sets for measuring similarities, in 11th IEEE Symposium on Computers and Communications (ISCC '06), Pula-Cagliari, Sardinia, Italy, pp. 227-232, 2006.
18. A. K. Coskun, T. Simunic, Y. Leblebici, and G. De Micheli, A Simulation Methodology for Reliability Analysis in Multi-Core SoCs, in Proceedings of the Great Lakes Symposium on VLSI (GLSVLSI), Philedelphia, Pennsylvania, USA, pp. 95-99, 2006.
19. S. Murali, M. Coenen, A. Radulescu, K. Goossens, and G. De Micheli, Mapping and Configuration Methods for Multi-Use-Case Networks on Chips, in Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, vol. 1, pp. 146-151, 2006.

2005

1. N. Genko, D. Atienza, and G. De Micheli, NoC Emulation on FPGA: HW/SW Synergy for NoC Features Exploration, in Proceedings of the International Conference on Parallel Computing (ParCo 2005): Current & Future Issues of High-End Computing, Malaga, Spain, pp. 753-760, 2005.
2. T. Simunic, K. Mihic, and G. De Micheli, Optimization of Reliability and Power Consumption in Systems on a Chip, in International Workshop on Power and Time Modeling, Optimization and Simulation (PATMOS), Leuven, Belgium, pp. 237-246, 2005.
3. N. Genko, D. Atienza, G. De Micheli, L. Benini, J. Mendias, R. Hermida, and F. Catthoor, A Novel Approach for Network on Chip Emulation, in IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2365-2368, Kobe, Japan, 2005.
4. S. Yoon, L. Benini, and G. De Micheli, Finding Co-Clusters of Genes and Clinical Parameters, in 27th Annual International Conference of IEEE Engineering in Medicine and Biology Society (EMBC 2005), Shanghai, China, 2005.
5. S. Yoon and G. De Micheli, Prediction and Analysis of Human MicroRNA Regulatory Modules, in 27th Annual International Conference of IEEE Engineering in Medicine and Biology Society (EMBC 2005), Shanghai, China, 2005.
6. S. Yoon and G. De Micheli, Prediction of Regulatory Modules Comprising MicroRNAs and Target Genes, in Joint Meeting of the 4th European Conference on Computational Biology/6th Meeting of the Spanish Bioinformatics Network (ECCB 2005), Madrid, Spain, (Bioinformatics, vol. 21, suppl. 2, pp. ii93-ii100), 2005.
7. F. Worm, P. Thiran, G. De Micheli, and P. Ienne, Self-Calibrating Networks-On-Chip, in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Kobe, Japan, pp. 2361-2364, 2005.
8. T. Simunic, W. Qadeer, and G. De Micheli, Managing Heterogeneous Wireless Environments via Hotspot Servers, in Multimedia Computing and Networking (MMCN), San Jose, California, USA, pp. 110-123, 2005.
9. S. Murali and G. De Micheli, An Application-Specific Design Methodology for STbus Crossbar Generation, in Design, Automation and Test in Europe (DATE), Munich, Germany, pp. 1176-1181, 2005.
10. N. Genko, D. Atienza, G. De Micheli, J. Mendias, R. Hermida, and F. Catthoor, A Complete Network-On-Chip Emulation Framework, in Design, Automation and Test in Europe (DATE), Munich, Germany, no. 1, pp. 246 - 251, 2005.
11. S. Stergiou, F. Angiolini, S. Carta, L. Raffo, D. Bertozzi, and G. De Micheli, XPipes Lite: a Synthesis Oriented Design Library for Networks on Chips, in Design, Automation and Test in Europe (DATE), Munich, Germany, vol. 2, pp. 1188-1193, 2005.
12. S. Murali, L. Benini, and G. De Micheli, Mapping and Physical Planning of Networks-on-Chip Architectures with Quality-of-Service Guarantees, in Proceedings of the 10th Asia Pacific Design Automation Conference (ASP-DAC), Shanghai, China, vol. 1, pp. 27-32, 2005.
13. R. Tamhankar, S. Murali, and G. De Micheli, Performance Driven Reliable Link Design for Networks on Chips, in Proceedings of the 10th Asia Pacific Design Automation Conference (ASP-DAC), Shanghai, China, vol. 2, pp. 749-754, 2005.

2004

1. A. Jalabert, S. Murali, L. Benini and G.De Micheli, XpipesCompiler: A Tool for instantiating Application-Specific Networks on Chips, DATE, International Conference on Design and Test Europe, 2004, pp. 884-889
2. S.Murali and G.De Micheli, Bandwidth-Constrained Mapping of Cores pnto NoC Architectures, , DATE, International Conference on Design and Test Europe, 2004, pp. 896-901.
3. S. Yoon, C, Nardini, L. Benini and G. De Micheli, Enhanched P-Clustering and its Applications to Gene Espression Data BIBE, 2004, pp. 275-282.
4. G. De Micheli Reliable Communication in Systems on Chip DAC, Design Automation Conference, 2004, p. 77.
5. S. Murali and G. De Micheli, SUNMAP: A Tool for Automatic Toplogy Selection and Generation for NoCs DAC, Design Automation Conference, 2004, pp. 914-919.
6. K. Mihic, T. Simunic and G. De Micheli, Reliability and Power Management of Integrated Systems DSD, Euromicro Symposium on Digital Circuit Design, 2004, pp. 5-11.
7. S. Yoon and G. De Micheli, An Application of Zero-Suppressed Binary Decision Diagrams to Clustering Analysis of DNA MicroArray Data EMBS, Proceedings of the 26th Annual International Conference, 2004, pp. 2925-2929.

2003

1. A. Peymandoust, L. Pozzi, P. Ienne, G. De Micheli, Automatic instruction set extension and utilization for embedded processors, Proceedings, IEEE International Conference on Application-Specific Systems, Architectures and Processors, June 2003, pp. 103-114
2. T. Tao Ye, G. De Micheli, Physical planning for on-chip multiprocessor networks and switch fabrics, IEEE International Conference on Application-Specific Systems, Architectures and Processors, June 2003, pp. 92-102
3. G. De Micheli, Robust system design with uncertain information, Proceedings of First ACM and IEEE International Conference on MEMOCODE '03, June 2003, pp. 283
4. T. Tao Ye, L. Benini, G. De Micheli, Packetized On-Chip Interconnect Communication Analysis for MPSoC, Proceedings of Design Automation and Test in Europe, DATE, March 2003, pp. 344-349
5. G. De Micheli, Designing Robust System with Uncertain Information, Proceedings of ASPDAC, January 2003, pp. vi-vii.

2002

1. F. Worm, P. Thiran, P. Ienne and G. De Micheli, An Adaptive Low-power Transmission Scheme for On-chip Networks, ISSS, International Symposium on Systems Synthesis, Kyoto, Japan, October 2002, pp. 92-100
2. T. Ye, S. Chaudhuri, H. Savoj and G. De Micheli, Physical Synthesis for ASIC Datapath Circuits, ISCAS, International Symposium on Circuits and Systems, Vol. 3, pp.365-368, Tempe, 2002
3. E.Y. Chung, L. Benini, and G. De Micheli, Contents Provider Assisted Dynamic Voltage Scaling for Low Energy MultiMedia Applications, ISPLED, IEEE Symposium on Low Power Electronics and Design, 2002, pp. 42-47
4. T. Ye and G. De Micheli, Analysis of Power Consumption on Switch Fabrics in Network Routers, DAC-Proceedings of the Design Automation Conference, 2002, pp. 524-530
5. A. Peymandoust, T. Simunic and G. De Micheli, Complex Library Mapping for Embedded Software Using Symbolic Algebra, DAC-Proceedings of the Design Automation Conference, 2002, pp. 325-330
6. A. Peymandoust, T. Simunic and G. De Micheli, Low-Power Embedded Software Optimization Using Symbolic Algebra, DATE, International Conference on Design and Test in Europe, Paris, 2002, pp. 1052-1058
7. D. Bertozzi, L. Benini and G. De Micheli, Low Power Error-Resilient Encoding for On-Chip Data Buses, DATE-International Conference on Design and Test in Europe, Paris, 2002, pp. 102-109
8. L. Benini and G. De Micheli, Networks on Chip: A New Paradigm for Systems on Chip Design, DATE-International Conference on Design and Test in Europe, Paris 2002, pp. 418-419

2001

1. A. Peymandoust and G. De Micheli, Symbolic Algebra and Timing Driven Data-Flow Synthesis, ICCAD, Proceedings of the International Conference on Computer Aided Design, San Jose, CA, November 2001, pp. 300-305
2. P. Panda, L. Semeria and G. De Micheli, Cache-Efficient Memory Layout of Aggregate Data Structures, ISSS, Proceedings of the International Symposium on System Synthesis, Montreal, October 2001, pp. 101-106
3. E.Y. Chung, L. Benini and G. De Micheli, Source Code Transformation Based on Software Cost Analysis, ISSS, Proceedings of the International Symposium on System Synthesis, Montreal, October 2001, pp. 153-158
4. L. Benini and G. De Micheli, Powering Networks on Chips: Energy-Efficient and Reliable Interconnect Design for SoCs, ISSS, Proceedings of the International Symposium on System Synthesis, Montreal, October, 2001, pp. 33-38
5. E.Y. Chung, L. Benini and G. De Micheli, Automatic Source Code Specialization for Energy Reduction, ISLPED, IEEE Symposium on Low Power Electronics and Design, 2001, pp. 80-83
6. A. Peymandoust and G. De Micheli, Using Symbolic Algebra in Algorithmic DSP Synthesis, DAC-Proceedings of the Design Automation Conference, 2001, pp. 277-282
7. T. Simunic, L. Benini, A. Acquaviva, P. Glynn and G. De Micheli, Dynamic Voltage Scaling and Power management for Portable Systems, DAC-Proceedings of the Design Automation Conference, June 2001, pp. 524-529
8. T. Zhang, G. De Micheli and L. Benini, Component Selection and matching for IP-Based Design, DATE, Proceedings of the Design and Test in Europe, March 2001, pp. 40-46

2000

1. T. Ye and G. De Micheli, Data Path Placement with Regularity, ICCAD, Proceedings of the International Conference on Computer Aided design, San Jose, CA, November 2000, pp. 264-270
2. Y. H. Lu, L. Benini and G. De Micheli, Requester-Aware Power Reduction, ISSS, Proceeding of the International Symposium on System Synthesis, September 2000, pp. 18-23
3. T. Simunic, L. Benini, G. De Micheli and M. Hans, Source Code Optimization and Profiling of Energy Consumption in Embedded Systems, ISSS, Proceedings of the International Symposium on System Synthesis, September 2000, pp. 193-198
4. T. Simunic, L. Benini, P. Glynn and G. De Micheli, Dynamic Power Management for Portable Systems, MOBICOM, Proceeding of the International Conference on Mobile Computing and Networking, August 2000, pp. 11-19
5. T. Simunic, H. Vikalo, P. Glynn and G. De Micheli, Energy Efficient Design of Portable Wireless Systems, ISLPED, IEEE Symposium on Low Power Electronics and Design, 2000, pp. 49-54
6. Y. Lu, L. Benini and G. De Micheli, Operating System Directed Power Reduction, ISLPED, IEEE Symposium on Low Power Electronics and Design, 2000, pp. 37-42
7. Y. Lu, L. Benini and G. De Micheli, Low-Power Task Scheduling for Multiple Devices, CODES, Proceedings of the IEEE Hardware/Software C-Design Workshop, 2000, pp. 39-43
8. L. Semeria, K. Sato and G. De Micheli, Resolution of Dynamic Memory Allocation and Pointers for the Behavioral Synthesis from C, DATE, Proceedings of the Design Automation and Test in Europe, March 2000, pp. 312-319
9. T. Simunic, L. Benini, P. Glynn and G. De Micheli, Dynamic Power Management of Laptop Hard Disk, DATE, Proceedings of the Design Automation and Test in Europe, March 2000, pp. 736
10. Y. Lu, E.Y. Chung, T. Simunic, L. Benini and G. De Micheli, Quantitive Comparison of Power Management Algorithms, DATE, Proceedings of the Design Automation and Test in Europe, March 2000, pp. 20-26

1999

1. T. Suminic, L. Benini and G. De Micheli, Event-Driven Power Management of Portable Systems, ISSS, Proceedings of International Symposium od System Synthesis, November 1999, pp. 18-23
2. E.Y. Chung, L. Benini and G. De Micheli, Dynamic Power Management Using Adaptive Learning Tree, ICCAD, Proceedings of the International Conference on Computer Aided design, San Jose, CA, November 1999, pp. 274-279
3. Y. Sasaki and G. De Micheli, Cross-talk Delay Analysis Using Relative Window Method, IEEE International ASIC/SOC Conference 1999, pp. 9-13
4. J. Smith and G. De Micheli, A Methodology for Synthesis with Re-Usable Components from Arithmetic Specification, ECCTD, Proceedings of the European Conference on Circuit Theory and Design Stress, Vol. 2, 1999, pp. 1195-1198
5. L. Benini and G. De Micheli, System-Level Power Optimization: Techniques and Tools, ISLPED, IEEE Symposium on Low Power Electronics and Design, 1999, pp. 288-293
6. A. Bogliolo, L. Benini, G. De Micheli and B. Ricco, Efficient Switching Activity Computation During High-Level Synthesis of Control-Dominated Designs, ISLPED, IEEE Symposium on Low Power Electronics and design, 1999, pp. 127-132
7. T. Simunic, L. Benini and G. De Micheli, Energy-Efficient Design of Battery-Powered Embedded Systems, ISLPED, IEEE Symposium on Low Power Electronics and Design, 1999, pp. 212-217
8. L. Benini, G. de Micheli, E. Macii, G. Odasso and M. Poncino, Kernel-based Power Optimization of RTL Components: Exact and Approximate Extraction Algorithms, DAC-Proceedings of the Design Automation Conference, 1999, pp. 247-252
9. T. Simunic, L. Benini and G. De Micheli, Cycle-Accurate Simulation of energy Consumption in Embedded Systems, DAC-Proceedings of the design Automation Conference, 1999, pp. 867-872
10. Y. H. Lu, T. Simunic and G. De Micheli, Software Controlled Power Management, CODES, Proceeding of the IEEE Hardware/Software C-design Workshop, 1999, pp. 157-161
11. Y. H. Lu and G. De Micheli, Adaptive Hard Disk Power Management on Personal Computers, Proceedings of the IEEE Great Lakes Symposium, 1999, pp. 50-53
12. G. De Micheli, Hardware Synthesis from C/C++ Models, DATE, Proceedings of the Design Automation and test in Europe Conference, 1999, pp. 382-383
13. L. Benini, G. De Micheli, A. Macii, E. Macii and R. Scarsi, Glitch Power Minimization by Gate Freezing, DATE, Proceeding of the Design Automation and Test in Europe Conference, 1999, pp. 163-167
14. E. Y. Chung, L. Benini and G. De Micheli, Dynamic Power Management for Non-Stationary Service Requests, DATE, Proceedings of the Design Automation and Test in Europe Conference, 1999, pp. 77-81
15. J. Smith and G. De Micheli, Polynomial Methods for Allocating Complex Components, DATE, Proceeding of the Design Automation and Test in Europe Conference, 1999, pp. 217-222

1998

1. L. Benini, A. Bogliolo and G. De Micheli, Dynamic Power Management of Electronic Systems, ICCAD, Proceedings of the International Conference on Computer Aided Design, San Jose, CA, November 1998, pp. 696-702
2. J. Smith and G. De Micheli, Polynomial Methods for Component Matching and Verification, ICCAD, Proceedings of the International Conference on Computer Aided Design, San Jose, CA, November 1998, pp. 678-685
3. L. Semeria and G. De Micheli, SpC: Synthesis of Pointers in C, Application of Pointer Analysis to the Behavioral Synthesis from C, ICCAD, Proceedings of the International Conference on Computer Aided Design, San Jose, CA, November 1998, pp. 340-346
4. S. Minato and G. De Micheli, Finding All Simple Disjunctive Decompositions Using Irredundant Sum-of Products Forms, ICCAD, Proceedings of the International Conference on Computer Aided Design, San Jose, CA, November 1998, pp. 111-117
5. V. Mooney, D. Ruspini, O. Kathib and G. De Micheli, Hardware/Software Run-Time Systems and Robotics: A Case Study, Proceedings of the EUROMICRO Conference, Vasteras, Sweden, 1998, pp. 162-167
6. M. Platzner and G. De Micheli, Acceleration of Satisfiability Algorithms by Reconfiqurable Hardware, FPL '98, Proceedings International Workshop of Field Programmable Logic and Applications, published as R. Hartenstein and Andres, Editors, Lecture Notes in Computer Science, No. 1482, Springer, 1998, pp. 69-78
7. L. Benini, G. De Micheli, A. Lioy, E. Macii, G. Odasso and M. Poncini, Computational Kernels and their Application to Sequential Power Optimization, DAC-Proceedings of Design Automation Conference, 1998, pp. 764-769
8. J. Smith and G. De Micheli, Automated Composition of Hardware Components, DAC-Proceedings of the Design Automation Conference, 1998, pp. 14-19
9. G. Paleogo, L. Benini, A. Bogliolo and G. De Micheli, Policy Optimization for Dynamic Power Management, DAC- Proceedings of the Design Automation Conference, 1998, pp. 182-187
10. L. Benini, F. Vermuelen and G. De Micheli, Finite State Machine Partitioning for Low Power, ISCAS, Proceedings of the International Symposium on Circuits and Systems, Vol. II, June 1998, pp. 5-9
11. H. Kapadia, G. De Micheli and L. Benini, Reducing Switching Activity on Datapath Buses with Control-Signal Gating, CICC-Proceedings of the Custom Integrated Circuit Conference, 1998, pp. 589-592
12. L. Benini, G. De Micheli, E. Macii, D. Scuito and C. Silvano, Address Bus Encoding Techniques for System-Level Power Optimization, DATE, Proceedings of the Design Automation and Test in Europe Conference, 1998, pp. 861-866
13. A. Bogliolo, L. Benini and G. De Micheli, Characterization-Free Behavioral Power Modeling, DATE, Proceedings of the Design Automation and test in Europe Conference, 1998, pp. 767-773
14. L. Benini, G. De Micheli, A. Lioy, E. Macii, G. Odasso and M. Poncino, Timed Supersetting and the Synthesis of Large Telescopic Units, GLS-VLSI-98: IEEE/ACM 8th Great Lakes Symposium on VSLI, Lafayette, LA, February 1998, pp. 331-337
15. L. Benini, G. De Micheli, E. Macii, A. Macii, M. Poncino, Reducing Power Consumption of Dedicated Processors Through Instruction Set Encodingi IEEE/ACM 8th Great Lakes Symposium on VSLI, Lafayette, LA, February 1998, pp. 8-12

1997

1. L. Benini, G. De Micheli, A. Macii, E. Macii and M. Poncini, Fast Power Estimation for Determinator Input Streams ICCAD, Proceeding of the International Conference on Computer Aided Design, San Jose, CA, November 1997, pp. 494-501
2. P. Vuillod, L. Benini and G. De Micheli, Generalized Matching from Theory to Applications, ICCAD, Proceedings of the International Conference on Computer Aided Design, San Jose, CA, 1997, pp. 13-20
3. V. Mooney and G. De Micheli, Real Time Analysis and Priority Scheduler Generation for Hardware/Software Systems with a Synthesized Run-Time System, ICCAD, Proceedings of the International Conference on Computed Aided Design, San Jose, CA, 1997, pp. 605-612
4. C. Coelho, A. Fernandes and G. De Micheli, Reducing Coding Style Effects in High-Level Specifications, SBCCI, Proceedings of X Brazilian Symposium on Integrated Circuit Design, Gramado, Brazil, 1997, pp. 273-282
5. P. Vuillod, L. Benini and G. De Micheli, Re-Mapping for Low Power Under Timing Constraints, ISLPED, IEEE Symposium on Low Power Electronics and Design, 1997, pp. 287-292
6. L. Benini, G. De Micheli, E. Macii, M. Poncico and S. Quer, System-Level Power Optimization of Special Purpose Applications: The Beach Solution, ISLPED, IEEE Symposium on Low Power Electronics and Design, 1997, pp. 24-29
7. V. Mooney, T. Sakamoto and G. De Micheli, Run-Time Scheduler Synthesis for Hardware/Software Systems and Application to Robot Control Design, CODES/CASHE, Proceedings of the International Workshop on Hardware/Software Co-design,Braunschweig, 1997, pp. 95-99
8. A. Bogliolo, L. Benini and G. De Micheli, Adaptive Least Mean Square Behavioral Power Modeling, EDTC, Proceedings of the European Design and Test Conference, Paris, 1997, pp. 404-410
9. L. Benini, G. De Micheli, E. Macii, M. Poncino and R. Scarsi, Symbolic Synthesis of Clock-Gating Logic for Power Optimization of Control Oriented Synchronous Networks, EDTC, Proceedings of the European Design and Test Conference, Paris, 1997, pp. 514-520
10. L. Benini, G. De Micheli, E. Macii, D, Scuito and C. Silvano, Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems, Proceedings of the Great lakes Symposium on VSLI, March 1997, pp. 77-82
11. R. Bushroe, M. Pedram, R. Camposano, G. De Micheli, A. Domic, C. Hsu and M. Jackson, Physical Design and Synthesis (panel): Merge or Die!, ACM/IEEE Design Automation Conference, Anaheim, CA 1997, pp. 238-239