Emerging technologies and nanoscale computing fabrics

Wednesday, 10 July 2013 at 11h00 in room INF 328

Ian O'Connor, Lyon Institute of Nanotechnology, France

Abstract:
The advent of high-performance computing architectures is necessary to follow Moore's Law and allow the execution of future software applications both in terms of resolution (audio, video and scientific computing) and in terms of computing power or MIPS (real-time coding/decoding, data encryption/decryption). However, the use of conventional technologies will lead to several device-level hurdles (leakage currents, interconnect limitations, quantum effects …) It is widely recognized that conventional technology scaling will at some point break down in the face of these limits, both for fundamental and for economic reasons. Alternatives must be found, at both architectural and device levels. In this context, the emergence of new communication technologies (silicon photonics, 3D TSVs) and switching devices based on nanotubes (CNFET) or nanowires (NWFET) offers the opportunity to provide novel logic building blocks, to explore new possibilities for digital design and consequently to reconsider the paradigms of computing architectures to achieve orders of magnitude improvements in conventional figures of merit.

In this talk, I will look at the emergence of such technologies and present research led in the Heterogeneous Systems Design group at the Lyon Institute of Nanotechnology, to assess their potential in the context of computing and communication in future reconfigurable computing platforms. I will firstly present technologies capable of building large regular structures out of silicon nanowires or carbon nanotubes, and how logic functions can be mapped onto them, particularly in the context of reconfigurable applications. Some pointers to the future evolution of these technologies, enabling design techniques and associated architectures will be given, as well as the issues that must be solved before nanoscale computing fabrics become a viable alternative to CMOS. I will then look at predictive design technology for 3D integration technology, to evaluate the impact of technological characteristics on system performance, as well as to explore constraint propagation from application to technology. Finally, I will present a heterogeneous integration approach for a photonics communication layer in multicore computing architectures, as well as the expected gain in performance for both point to point links and for wavelength-routing networks on chip.

About the speaker: Ian O'Connor (IEEE S'95-M'98-SM'07) is Professor for Heterogeneous and Nanoelectronics Systems Design in the Department of Electronic, Electrical and Control Engineering at Ecole Centrale de Lyon, France. He is currently head of the Heterogeneous Systems Design group at the Lyon Institute of Nanotechnology, of which he is also one of the vice-directors. Since 2008, he also holds a position of Adjunct Professor at Ecole Polytechnique de Montréal, Canada.

His research interests include design methods and tools for physically heterogeneous systems on chip, and their application to novel system architectures based on non-conventional devices. He has authored or co-authored around 100 book chapters, journal publications and conference papers and has been workpackage leader or scientific coordinator for several national and european projects. He also serves as an expert with the French Observatory for Micro and Nano Technologies (OMNT), IFIP WG10.5 and ALLISTENE.