Multi-Unit Global Energy Management and Optimization for Network-on-Chip Applications

Zeynep Toprak, PhD Assistant at EPFL-STI-LSM

Abstract: The problem of energy optimization in multi-core systems (such as single-chip multiprocessors) where the individual energy demands of various processing elements are governed by instantaneous workload requirements is well defined in literature. The significance of the problem is underlined by the increasing prominence of multi-core systems that must operate under strict power/energy budget constraints, both in mobile applications and in cases where special cooling arrangements can be very expensive. A range of solutions have been proposed over the last few years, which are mostly based on static, off-line calculation of a limited set of operating points in the form of optimum voltage and frequency assignments, that are subsequently chosen according to actual demands. Still, to our best knowledge, none of these studies have demonstrated an on-line solution to complex, multi-variable energy optimization problem which allows dynamic adjustment of individual operating frequencies and supply voltages of multiple processing elements. This thesis presents the design and silicon implementation of an analog-based energy optimizer unit, which is capable of dynamically adjusting power supply and clock frequencies of multiple embedded cores, tailored to the instantaneous workload information (computational task) and fully adaptive to variations in process and temperature.

Our approach borrows from the basic principles of analog computation to continuously optimize the system-wide energy dissipation of multiple processing elements, converging on the global minima of the constrained optimization problem which are represented as stable operating points of a simple feedback loop. It is already well known that stable, approximate solutions of multi-variable optimization problems (such as gradient descent) can be obtained by using very compact analog circuits, e.g. resistive networks. The analogy between the energy minimization problem under timing constraints in a general task graph and the power minimization problem under Kirchhoff's current law constraints in an equivalent resistive network is exploited. The implementation of the on-line analog optimizer is then discussed. The realization of the blocks composing the system architecture is described, and circuit design issues are studied thoroughly.

About the speaker: Zeynep Toprak received her B.S. degree in Electronics and Telecommunication engineering from Istanbul Technical University in 1999. From November 1999 to July 2002 she worked as an analog design engineer at Alcatel Microelecronics R&D group in Turkey, where she contributed to design, layout and verification of several building blocks for various projects those can be listed as: DCDC converters, PLLs and VCXO. In September 2000 she joined Sabanci University (SU) as a graduated student. Her research topic was the realization of a Low-Power 200 MSample/s 12-bit Pipelined ADC Macro Using Deep-Submicron Digital CMOS Technology. She received her M.Sc. degree in Electronics Engineering in September 2001 from SU.

In July 2002, Zeynep joined ST Microelectronics in Turkey as an analog design engineer, where, she worked in design and layout of Data and Clock Recovery sub-block of a data communication chip, which is aimed for interfacing at physical layers E3, T3 and full custom data transmission. In January 2003 she joined CSEM (Centre Suiss Electronique et Microtechnique), where, she was involved in back-end design of three different regulators for PA, VCO and digital, two step-up circuits and RC oscillator sub-blocks for a wireless communication node operated on two switching AA batteries. Currently, she is a PhD student at Ecole Polytechnique Fédérale de Lausanne (EPFL).