Error-Aware Design

Fadi Kurdahi, Department of Electrical and Computer Engineering, University of California, Irvine

Abstract: The universal underlying assumption made today is that Systems on chip must maintain 100% correctness regardless of the application. This work advocates the concept that some applications - by construction - are inherently error tolerant and therefore do not require this strict bound of 100 % correctness. In such cases, it is possible to exploit this tolerance by aggressively reducing the supply voltage, thereby reducing power consumption significantly. This approach is demonstrated on several case studies in imaging, video and wireless communication fields.

About the speaker: Fadi Kurdahi received his PhD from the University of Southern California in 1987. Since then, he has been a faculty at the Department of Electrical & Computer Engineering at UCI, where he conducts research in the areas of Computer Aided Design of VLSI circuits, high-level synthesis, and design methodology of large scale systems, and serves as the Associate Director for the Center for Embedded Computer Systems (CECS). He was Associate Editor for IEEE Transactions on Circuits and Systems II 1993-1995, Area Editor in IEEE Design and Test for reconfigurable computing, and served as program chair, general chair or on program committees of several workshops, symposia and conferences in the area of CAD, VLSI, and system design. He received the best paper award for the IEEE Transactions on VLSI in 2002, the best paper award in 2006 at ISQED, and three other distinguished paper awards at DAC, EuroDAC and ASP-DAC. He is a Fellow of the IEEE.

 

Presentation slides with audio