Combitgen: A new approach for creating partial bitstreams in Virtex-II Pro devices

Walter Stechele, Department of Electrical Engineering and Information Technology, Technical University of Munich, Germany

Abstract: Today's FPGAs (Field Programmable Gate Arrays) are widely used, but not to their full potential. In Virtex series FPGAs from Xilinx a special feature, the dynamic and partial reconfiguration is available. This feature enables a designer to create a system on chip with a static area and a reconfigurable part that can be exchanged during run-time while the remaining static portion is still operational. We present a new technique that combines the advantages of already existing partial dynamic reconfiguration flows for Xilinx Virtex FPGAs. The method reduces unnecessary frames in bitstreams without increasing their quantity. In our simple example design we could achieve an improvement of the reconfiguration times up to 8 percent compared to a common matchable reconfiguration method. Our approach also surpasses all Xilinx generated bitstreams in terms of reconfiguration times.

About the speaker: Walter Stechele received the Dipl.-Ing. and Dr.-Ing. degrees in electrical engineering from the Technical University of Munich, Germany, in 1983 and 1988, respectively. In 1990 he joined Kontron Elektronik GmbH, a German electronic company, where he was responsible for the ASIC and PCB design department. Since 1993 he has been Academic Director at the Institute for Integrated Systems at the Technical University of Munich. His interests include digital video processing and VLSI design, with focus on system-on-chip design methodology and low power implementation for mobile multimedia, dynamic reconfiguration of FPGAs, and applications in video-based driver assistance.

 

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