Pushing the energy-efficiency envelope: Designing ultra-low power equalized logic circuits and energy-efficient silicon-photonic NoC architectures

Thursday, 12 March 2015 at 15:00 in INF 328

Ajay Joshi, Boston University, Boston, Massachusetts, USA

 

Abstract:

Energy-efficiency has become a primary constraint in the design and operation of all types (biomedical implants, mobile systems, servers and data centers) of current and future computing systems. Hence, we need to develop design time and run time techniques at all levels in the design hierarchy to maximize the overall system energy efficiency. In this talk, I will first present a novel circuit-level approach that uses communication-inspired techniques for designing energy-efficient sub-threshold circuits for ultra-low power embedded systems. In the sub-threshold regime, process variations can result in up to an order of magnitude variations in Ion/Ioff ratios leading to timing errors. As a result it is not possible to operate the circuit at the minimum energy point. Therefore, there is a need to develop mechanisms to mitigate these timing errors. I will present a communications-inspired tunable adaptive feedback equalizer circuit that adjusts the switching thresholds of the gate before the flip flop based on the gate's output in the previous cycle. This enables a faster switching of the gate outputs, which mitigates timing errors. This mitigation of timing errors provides an opportunity to reduce the dominant leakage energy component and in turn improve the energy efficiency of the digital logic circuit and the system as a whole.

The second part of my talk will focus on architecture techniques for maximizing energy efficiency in manycore systems. To sustain the historic performance improvement in computing systems, the computing community has migrated towards manycore systems with the goal of improving the computing capacity per chip through parallelism while staying within the chip power budget. Energy-efficient data communication has been identified as one of key requirements for achieving this goal, and silicon-photonic network-on-chip (NoC) has been proposed as one of technologies that can meet this requirement. Silicon-photonic NoC provides high bandwidth density, but its large laser power consumption can negate this bandwidth density advantage. I'll present a run-time strategy that involves using cache and NoC reconfiguration to reduce laser power of the silicon-photonic NoC at run time, and in turn maximize the energy efficiency of the NoC and the system as a whole. The key idea here is to provide the minimum L2 cache and the minimum NoC bandwidth (i.e. the minimum number of active silicon-photonic links) required for an application to achieve the maximum possible performance at any given point of time.
 

About the speaker:

Ajay Joshi received his Ph.D. degree from the ECE Department at Georgia Tech in 2006. He then worked as a postdoctoral researcher in the EECS Department at MIT until 2009. He is currently an Assistant Professor with the ECE Department at Boston University. His research interests span across various aspects of VLSI design including circuits and architectures for communication and computation, and emerging device technologies including silicon photonics and memristors. He received the NSF CAREER Award in 2012 and Boston University ECE Department's Award for Excellence in Teaching in 2014.